Read Sharp UP-3500 (serv.man29) Service Manual online
UP-3500 (V)
HARDWARE DESCRIPTION
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7-2. OPERATION FLOW
■ Power ON / CKDC reset (Reset switch: Neighborhood of the expansion SRAM socket)
■ Power OFF
8. INTERRUPTION
The interruption is as shown below.
■ CPU port
■ FPGA
For USART, UART, and software interruption, refer to the item of the
FPGA.
POFF# cancel
NO
YES
CKDC sleep
Power ON
CKDC reset
CKDC boot
CKDC system reset cancel
FPGA configuration
FPGA DONE rising
CPU reset cancel
STOP# generates ?
Standby
POF detection
(CKDC,CPU)
YES or when STOP# does not generate for 100ms.
CKDC system reset execution
NO (up to 100ms)
CPU
I/O
External
signal name
Remark
IRL2
I
TOUCH_INT#
TOUCH PANEL INTRRUPT
IRL1
I
FPGAINT#
FPGA INTRRUPTUSART, UART,
CKDC, SOFT INT, LAN, MCR
CKDC, SOFT INT, LAN, MCR
IRL0
I
POFF#
POFF# signal
CMT/CTR3
I
CKDC_SHEN#
SHEN# signal
CMT/CTR3
I
MCRINT#
MCRINT# signal
FPGA
I/O
External
signal name
Remark
EXINT1#
I
KRQ#
CKDC interruption
EXINT2#
I
LANINT#
LAN controller interruption
EXINT3#
I
MCRINT#
MCR interruption
EXINT4#
I
SHEN#
CKDC SHIFT ENABLE
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