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6. Interface pin connection (LCD)
(1) CN1
Pin No.
Symbol
Function
1
FRAME
Frame signal
2
LOAD
Display data latch signal
3
CP
Display data shift lock
4
DOFF
LCD display control signal
H:ON, L:OFF
H:ON, L:OFF
5
V
DD
Logic circuit power voltage
6
V
SS
Reference voltage (GND)
7
V
O
LCD drive voltage
8
D0
Display data
9
D1
Display data
10
D2
Display data
11
D3
Display data
12
DF (N.C)
LCD drive signal (AC signal)
13
V
EE
(N.C)
LCD drive voltage
14
F.G (N.C)
Frame GND
7. Block diagram
The timing of each signal conforms to the LC7940ID segment driver
and the LC7943D common driver.
and the LC7943D common driver.
8. Interface timing
Switching characteristics
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
CP Frequency
fcp
Duty = 50%
—
—
6.0
MHz
CP Pulse Width
tw1
—
56
—
—
ns
LOAD Pulse Width
tw2
—
70
—
—
ns
CP Rize/Fall Time
tr,tf
—
—
—
50
ns
DATA Set Up Time
tDSU
—
35
—
—
ns
DATA Hold Time
tDHD
—
35
—
—
ns
CP Set Up Time
tESUI
—
80
—
—
ns
LOAD
→
CP Time
tLC
—
80
—
—
ns
FRAME Set Up
Time
Time
tsetup
—
100
—
—
ns
FRAME Hold Time
thold
—
100
—
—
ns
Com1
Y driver1
Com200
Y driver3
Y driver2
FRAME
X driver1
X driver2
Seg1
Seg640
X driver8
LCD
640 x 200DOTS
DOFF
A.C
LOAD
C P
D0~D3
F.G
VSS
BIAS
VD D
VO
A.C: Divided frequency circuit
BIAS: Voltage divide circuit
ON: Logic power ON
→
LCD power ON
OFF: LCD powerOFF
→
Logic power OFF
Note: Power source
1,1
D3
D3
1,2
D2
1,3
D1
1,4
D0
1,5
D3
2,1
D3
D3
2,2
D2
2,3
D1
2,4
D0
2,5
D3
200,1
D3
200,2
D2
200,3
D1
200,4
D0
200,5
D3
1,640
D0
2,640
D0
200,640
D0
1dot
2dot
3dot
4dot
5dot
1dot
2dot
200dot
(DATA MAP)
640dot
1,(1~640)
200
160
200,637
1,1
1,5
1,637
2,1
1
1
2
160
3
1
2
LORD
CP
D3
200,638
1,2
1,6
1,638
2,2
D2
200,639
1,3
1,7
1,639
2,3
D1
200,640
1,4
1,8
1,640
2,4
D0
1,(1~640)
200,(1~640)
1,(1~640)
LORD
D0~D3
FRAME
199
200
1
2
200
2
1
1
CP
0.8VDD
0.8VDD
tw1
tw1
ft
ft
0.2VDD
0.2VDD
tDSU
tDHD
0.8VDD
0.8VDD
tw1
0.8VDD
0.2VDD
0.8VDD
0.2VDD
0.2VDD
0.8VDD
0.8VDD
tw2
0.2VDD
tLc
tESU1
tr
tr
0.8VDD
0.8VDD
0.2VDD
0.2VDD
tsetup
thold
D0~D3
LOAD
FRAME
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