Read Sharp UP-600 / UP-700 (serv.man25) Service Manual online
17-1. CPU interface
The CPU interface for the USART (8251) and magnet card reader
(MCM-21) in the UP-600/700 system is shown below.
(MCM-21) in the UP-600/700 system is shown below.
Signal description
RCP1
TRACK 1 CLOCK PULSE
RDD1
TRACK 1 DATA SIGNAL
RCP2
TRACK 2 CLOCK PULSE
RDD2
TRACK 2 DATA SIGNAL
RCP3
TRACK 3 CLOCK PULSE
RCD3
TRACK 3 DATA SIGNAL
CLS1
TRACK 1 CARD DETECTION SIGNAL
CLS2
TRACK 2 CARD DETECTION SIGNAL
CLS3
TRACK 3 CARD DETECTION SIGNAL
RCVRDY1
TRACK 1 DATA RECEIVING SIGNAL
RCVRDY2
TRACK 2 DATA RECEIVING SIGNAL
RCVRDY3
TRACK 3 DATA RECEIVING SIGNAL
INTMCR
INTERRUPT SIGNAL OR-SYNTHESIZED from
RCVRDY and SYNC input
RCVRDY and SYNC input
2 chip select signals for 8251 are generated inside MPCA8.
17-2. MCR interface
The operating timing of the MCR interface signals is given below.
(1) Example of timing
(2) Detailed timing (relation between DATA and CLOCK PULSE)
The "NULL" CODE is basically written prior to the opening code. The
opening code detection algorithm is considered because data may
become corrupt before and after the CARD detection signal due to a
worn magnet stripe.
opening code detection algorithm is considered because data may
become corrupt before and after the CARD detection signal due to a
worn magnet stripe.
18. 1-HOLE CLERK
On the UP-600/700, 1-hole clerk key with up to 8 bits can be used.
The 1-hole clerk switch is controlled through the CKDC9 on the main
board.
board.
CPU
ICI
INTMCR
RCVRDY1
RCVCLK2
RDD1
RCP2
RDD2
CLS1
RCVDT1
RCP1
/DSR1
CLS2
RCVDT2
8251 x 2
Integrated as MPCA8
in the ER-A770 system.
in the ER-A770 system.
RCVCLK1
/DSR2
CLS1,
CLS2
RCVRDY1
RCVRDY2
INTMCR
SYNC
MPCA7
RCP1
CLS2
RCVRDY3
RCVRDY2
RDD3
RCVDT3
/DSR3
RCVCLK3
CLS3
RCP3
RDD1/RDD2
RCP1/RCP2
CLS1/CLS2
RDD3
RCP3
CLS3
"0" "1" "1"
Approx. 16µ s
Min. 5 µ s
RDD1/RDD2
RCP1/RCP2
RDD3
RCP3
CKDC9
ST0 ST3
LS138
X2
/S2 /S9
/CFSR
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