UP-600, UP-700 (serv.man25). UP600-700 Service Manual - Sharp ECR Service Manual (repair manual). Page 44

The address map of the total memory space is shown below. As you
can see, the memory space is divided into the following 5 blocks:

0page area (including the I/O area)

•

VRAM

•

RAM

•

ROM

•

Extended I/O area

The 0page area consists of four spaces: the ROM mapped area,
internal and external I/O areas. 
The ROM mapped space have been devised for the following pur-
poses:

Simplifying the procedure for booting the IPL program

Achieving high-speed accessing, and accessing by abbreviated
instructions.

The addresses from 00FF80h to 00FFFFh are called the internal I/O
area.
The internal I/O area is a space where the control registers and
built-in ports inside the CPU are addressed.
The external I/O area is a space where the peripheral devices outside
the CPU or devices on an optional card are addressed.

000000h

0 page area

(64KB)

00FFFFh

200000h

600000h

800000h

C00000h

C20000h

F00000h

FFFFFFh

Extended I/O area

(1MB)

(2MB)

Flash

EXTEND RAM

(4MB)

STD RAM (2MB)

(4MB)

VRAM (128KB)

EP-ROM

D00000h

* The expanded I/O area means
  the space for the I/O device
  addressed in the area excluding
  the 0 page one.
  MPCA8 uses FFFF00h to 
  FFFFFFh for the addressed
  register (BAR) of SSP. 
 The I/O register for VGAC is
  included.

* In the 0 page area, lower 64KB
  or less of the flash area is 
  mapped.
  By mapping the ROM area, the
  reset start and other vectors
  become addressable.

000000h

00FFFFh

00FF80h

00FE80h

Internal I/O area

External I/O area

ROM mapping area

I/O area

* The ROM area 200000h to
  20FFFFh (ROS1 lower 64KB)
  is mapped on the ROMmapping
  area.

* The internal I/O area is used
  for peripheral modules inside
  the CPU; the external I/O area
  is used for peripheral modules
  outside the CPU.
  For more information, refer to
  the H8/510 hardware manual
  and peripheral device
  specification.

00FE80h

00FF80h

00FFA0h

00FFB0h

00FFB4h

00FFB8h

00FFBCh

00FFC0h

00FFD0h

00FFE0h

00FFF0h

00FFFFh

Internal I/O area

MPCCS

MCR1Z

MCR2Z

OPCCS2

OPCCS1

T/PZ

OPTCSZ

Expanded MPC

(not used)

MCR3Z

CPCSZ (not used)

TPRC1

* CPCSZ is CPC select for
  Centronics Interface.

* MPCCS and expanded MPC
  signals are base signals for
  MPCA9 internal register
  decode. There is no external
  signal.

* MCR1Z, MCR2Z and MCR3Z

* MCR1Z and MCR2Z are chip

 are chip select signals for the

   magnet card reader.
  (Use lower 2bytes.)

* T/PZ is the internal decode
  signal for USART built in
  MPCA9. Thereis no external
  signal. (Use lower 2bytes.)

* OPCCS1 and OPCCS2
  signals are decoded inside
  the OPC (OPTION PERIP-
  HERAL CONTROLLER)
  using the option decode
  signal OPTCS. There is no
  external signal.

TPRC1 is built in by
MPCA9.