Read Sharp UP-600 / UP-700 (serv.man20) Service Manual online
No.
CPU
Signal
name
I/O
Remarks
30
IOWB
/MWE
I
Memory Write
31
SMEMRB
SMEMRB
I
N.U. (Pull-Up)
32
SMEMWB
SMEMWB
I
N.U. (Pull-Up)
33
RSTDRV
RSTDRV
I
Hardware Reset
34
AEN
/CS3
I
Chip Select
35
IOCHRDY
/WAIT
O
Wait to CPU
36
SD0
LD0
I/O
DATA Bus
37
SD1
LD1
I/O
38
SD2
LD2
I/O
39
SD3
LD3
I/O
40
SD4
LD4
I/O
41
SD5
LD5
I/O
42
SD6
LD6
I/O
43
SD7
LD7
I/O
44
GND
GND
45
TPOUT+
TPOUT+
O
10Base-T output +
46
TPOUT-
TPOUT-
O
10Base-T output -
47
VDD
+5V
48
TX-
TX-
O
N.U. (Pull-Down)
49
TX+
TX+
O
N.U. (Pull-Down)
50
X1
X1
I
Oscillator connection terminal
51
X2
X2
O
Oscillator connection terminal
52
GND
GND
53
CD-
CD-
I
N.U. (OPEN)
54
CD+
CD+
I
N.U. (OPEN)
55
RX-
RX-
I
N.U. (OPEN)
56
RX+
RX+
I
N.U. (OPEN)
57
VDD
+5V
58
TPN-
TPIN-
I
10Base-T input -
59
TPN+
TPIN+
I
10Base-T input +
60
LEDBNC
LEDBNC
O
N.U. (OPEN)
61
LED0
LED0
O
N.U. (OPEN)
62
LED1
LED1
O
N.U. (OPEN)
63
LED2
LED2
O
N.U. (OPEN)
64
AUI
AUI
I
GND
65
JP
JP
I
Pull-Up
66
PNP
PNP
I
OPEN
67
BS0
BS0
I
OPEN
68
BS1
BS1
I
OPEN
69
BS2
BS2
I
OPEN
70
VDD
+5V
71
BS3
BS3
I
OPEN
72
BS4
BS4
I
OPEN
73
BA15
BA15
O
N.U. (OPEN)
74
PL0
PL0
I
OPEN
75
BCSB
BCSB
O
N.U. (OPEN)
76
EECS
EECS
O
N.U. (OPEN)
77
PL1
PL1
I
OPEN
78
IRQS0
IRQS0
I
OPEN
79
IRQS1
IRQS1
I
OPEN
80
IRQS2
IRQS2
I
OPEN
81
IOS0
IOS0
I
OPEN
82
IOS1
IOS1
I
OPEN
83
GND
GND
84
IOS2
IOS2
I
OPEN
85
IOS3
IOS3
I
OPEN
86
GND
GND
87
SD15
SD15
I/O
N.U. (Pull-Down)
88
SD14
SD14
I/O
N.U. (Pull-Down)
89
VDD
+5V
90
SD13
SD13
I/O
N.U. (Pull-Down)
91
SD12
SD12
I/O
N.U. (Pull-Down)
92
SD11
SD11
I/O
N.U. (Pull-Down)
No.
CPU
Signal
name
I/O
Remarks
93
SD10
SD10
I/O
N.U. (Pull-Down)
94
SD9
SD9
I/O
N.U. (Pull-Down)
95
SD8
SD8
I/O
N.U. (Pull-Down)
96
SLOT16
SLOT16
I
Pull-Down
97
INT7
INT7
O
N.U. (Pull-Down)
98
INT6
INT6
O
N.U. (Pull-Down)
99
INT5
INT5
O
N.U. (Pull-Down)
100
INT4
INT4
O
N.U. (Pull-Down)
Note: Signals suffixed with the letter "B" are active in low level.
CHAPTER 5. MEMORY MAP
Flash
SRAM
CS0 SPACE
CS1 SPACE
CS2 SPACE
CS3 SPACE
Dual-Port SRAM
LAN Controller
H'FFFFFFFF
H'FFFFF000
H'FFFF8800
H'FFFF8000
H'02000000
H'01000000
H'00C*****
H'00C00000
H'00800FFF
H'00800000
H'00407FFF
H'00400000
H'0007FFFF
H'00000000
DRAMS space
Reserved
Reserved
Built-in peripheral
Module
Built-in RAM
2 The CS1 space is a physical
space of 4 MB. Is uses LA0~LA14
alone and thus LAP AROUND
occurs.
The data bus size is 8 bits.
space of 4 MB. Is uses LA0~LA14
alone and thus LAP AROUND
occurs.
The data bus size is 8 bits.
1 The CS0 space is a physical
of 4 MB. It uses LA0~LA16
alone and thus LAP AROUND
occurs.
In addition, the data bus size is
set to 8 bits using the operation
mode setting terminal of the CPU.
of 4 MB. It uses LA0~LA16
alone and thus LAP AROUND
occurs.
In addition, the data bus size is
set to 8 bits using the operation
mode setting terminal of the CPU.
3 The CS2 space is a physical
space of 4 MB. It uses LA0~LA11
alone and thus LAP
AROUND occurs.
The data bus size is 8 bits.
space of 4 MB. It uses LA0~LA11
alone and thus LAP
AROUND occurs.
The data bus size is 8 bits.
4 The CS3 space is a physical
space of 4 MB. Is uses LA0~LA19
alone and thus LAP AROUND
occurs.
The data bus size of the LAN
controller is fixed to 8 bits.
space of 4 MB. Is uses LA0~LA19
alone and thus LAP AROUND
occurs.
The data bus size of the LAN
controller is fixed to 8 bits.
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