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3. RAM control
/WE:
Write signal
When the signal is low, writing is performed. When the
signal is high, reading is performed.
When the signal is low, writing is performed. When the
signal is high, reading is performed.
/CE:
Chip select signal
A8-A14: Address bus
AD0-7:
Address/Data bus
A0-1:
Address bus signal
/ALE:
Address latch signal
Address signals A0-A7 are used commonly with the data bus. When
the address latch signal /ALE is input to IC3, the address/data bus
signal AD0-AD7 access the RAM as address signals A0-A7.
the address latch signal /ALE is input to IC3, the address/data bus
signal AD0-AD7 access the RAM as address signals A0-A7.
(READ)
As shown in the attached time chart, address signals are outputted
from P20-P27, P111-P117, and the lower address is latched with P32.
The modes at P20-P27 are changed to the input mode. The chip
enable signal (P31) is output for the RAM. Then the output data from
the RAM are read from P20-P27.
from P20-P27, P111-P117, and the lower address is latched with P32.
The modes at P20-P27 are changed to the input mode. The chip
enable signal (P31) is output for the RAM. Then the output data from
the RAM are read from P20-P27.
(WRITE)
As shown in the attached time chart, address signals are outputted
from P20-P27, P111-P117, and the lower address is latched with P32.
The write enable signal (P30) is output. The write data to the RAM are
output from P20-P27. Then the chip enable signal (P31) is output to
write the data.
from P20-P27, P111-P117, and the lower address is latched with P32.
The write enable signal (P30) is output. The write data to the RAM are
output from P20-P27. Then the chip enable signal (P31) is output to
write the data.
4. Printer control circuit (ER-A310)
1) Printer motor drive circuit
The motor drive signal MD from the CPU is used to operate the
printer motor with switching operation of transistor Q17.
printer motor with switching operation of transistor Q17.
IC2
CPU
IC3
74HC373
IC14
S-RAM
A8~A14
/ALE
A0~A7
AD0~AD7
AD0~AD7
/WE
/CE
P111~P117
P20~P27
P32
P30
RAM /OE
P31
P20~P27
(READ cycle)
Upper address
Lower address
RAM data output
15ns or above
15ns or
above
70ns or above
0ns or above
Lower address
latch signal
30ns or above
Fixed to HIGH.
Fixed to LOW
READ timing
Select
Input
Output
70ns or above
Hammer common
RAM control
RAM /WE
RAM /CS
P20~P27
P111~P117
P20~P27
P32
P30
RAM /OE
P20~P27
P20~P27
RAM Data IN
RAM control
(WRITE cycle)
Upper address
Lower address
Input data to RAM
15ns or above
15ns or
above
30ns or above
0ns or above
Lower address
latch signal
30ns or above
50ns or above
Fixed to LOW.
0ns or
above
60ns or
above
READ timing
Select
Input
Output
Hammer common
RAM /WE
RAM /CS
P20~P27
M
VP : +24V
M
R60
R61
Q17
C3784
IC2
CPU
MD
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