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Y, U and V). When the digital video output is progressive, the Vaddis 778 output analog
progressive video in components format only, through the three components DACs or
compatible interlaced video. The video encoder and DACs operate with a 54 MHz clock.
The audio output is 16, 18, 20 or 24 bits, two to eight channels, PCM samples at 16, 22.05, 24,
32, 44.1, 48, 96 or 192 KHz with each pair of (e.g., left and right) samples interleaved on a
serial bus according to several flavours of the I2S standard. Post processing of the decoded
audio and one stereo digital audio input, suitable for Karaoke and similar applications is
supported.
Audio coded data or reconstructed data can be output on a single line using an internal S/PDIF
transmitter. PCM or coded audio data can be also input through one of two S/PDIF (TTL)
inputs using a S/PDIF receiver to recover the input bit clock.
The Vaddis 778 can also output 8 bits, Y, U and V, 4:2:2, digital (“still”) video to the
HDXtreme companion chip, in various formats, compatible with the HDXtreme, as long as the
sample rate is less than 135 MHz and the width of the Y component is less than 2047. In this
mode, no other digital or analog video is output.
The Vaddis 778 uses Synchronous DRAMs (SDRAM) for external buffers and generates all
address and control signals for this external buffer. The required Synchronous DRAMs are of
- 7 type (max clock rate of 147 MHz). The required size is 64 Mbits using one 4M*16 bit
device. The internal structure of the devices has to be four banks of 2048 rows by 256 cells
each.
Some limited applications can be supported by a single or dual 16 Mbits device(s). A single
128 Mbits device with four banks of 2048 rows by 512 cells each is also supported.
The Vaddis 778 interfaces to the other devices of a player (e.g., IR remote control receiver,
front panel controller, audio DACs and ADCs) mainly through GPIO functions controlled by
SW to implement protocols like SPI and I2C. There are on-chip HW aids to interface to a
master SSC type device (e.g., a front panel concentrator).
progressive video in components format only, through the three components DACs or
compatible interlaced video. The video encoder and DACs operate with a 54 MHz clock.
The audio output is 16, 18, 20 or 24 bits, two to eight channels, PCM samples at 16, 22.05, 24,
32, 44.1, 48, 96 or 192 KHz with each pair of (e.g., left and right) samples interleaved on a
serial bus according to several flavours of the I2S standard. Post processing of the decoded
audio and one stereo digital audio input, suitable for Karaoke and similar applications is
supported.
Audio coded data or reconstructed data can be output on a single line using an internal S/PDIF
transmitter. PCM or coded audio data can be also input through one of two S/PDIF (TTL)
inputs using a S/PDIF receiver to recover the input bit clock.
The Vaddis 778 can also output 8 bits, Y, U and V, 4:2:2, digital (“still”) video to the
HDXtreme companion chip, in various formats, compatible with the HDXtreme, as long as the
sample rate is less than 135 MHz and the width of the Y component is less than 2047. In this
mode, no other digital or analog video is output.
The Vaddis 778 uses Synchronous DRAMs (SDRAM) for external buffers and generates all
address and control signals for this external buffer. The required Synchronous DRAMs are of
- 7 type (max clock rate of 147 MHz). The required size is 64 Mbits using one 4M*16 bit
device. The internal structure of the devices has to be four banks of 2048 rows by 256 cells
each.
Some limited applications can be supported by a single or dual 16 Mbits device(s). A single
128 Mbits device with four banks of 2048 rows by 512 cells each is also supported.
The Vaddis 778 interfaces to the other devices of a player (e.g., IR remote control receiver,
front panel controller, audio DACs and ADCs) mainly through GPIO functions controlled by
SW to implement protocols like SPI and I2C. There are on-chip HW aids to interface to a
master SSC type device (e.g., a front panel concentrator).
Features
1.2 Feature List
1.2.1 Disc Loader Control and Bitstream Processing
1.2 Feature List
1.2.1 Disc Loader Control and Bitstream Processing
-8 analog inputs (low frequency) for servo errors and RF signals envelope monitoring
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11 actuators drive or control outputs. Two analog outputs through 11 bits DACs (e.g., for the
tracking and focus coils), and 9 PWM, which can be used e.g., for sled and spindle motors,
programmed tray motion or RF amplifier parameter setting.
programmed tray motion or RF amplifier parameter setting.
-
Processing of spindle and sled position readback devices.
-
All servo loop closure, closed loop control, disc identification and error handling.
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Bitstream extraction using AGC, bit clock frequency detection and phase lock loop, adaptive
threshold calculations, Viterbi bit decision, defect detection, frame sync detection and EFM/P
conversion.
conversion.
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CD sub-code extraction and processing.
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CD ECC for all CD types. CD EDC for Mode 1 discs.
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DVD ECC and EDC.
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Track buffer and re-try management.
1.2.2 Decoding
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Single chip solution for playback of DVDVideo, DVD-Audio Video-CD, Super Video-CD,
CD-DA, and MP3, AAC, WMA, MPEG 4, DivX or JPEG from flash cards, DVD_ROM,
DVD-R, DVD-RW, CD-ROM, CD-R or CD-R/W discs.
DVD-R, DVD-RW, CD-ROM, CD-R or CD-R/W discs.
-
Decoding and display of high resolution JPEG, and standard resolution MPEG-4, DivX,
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