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are transferred through the MUX unit to the BSI. For the sectors for which the EDC (Error
Detection) function was performed, the EDC error indication is added at the end of the
sector data replacing the original 4 EDC bytes. For DVD discs, the ECC unit reads media data
from the SDRAM through the MCU and performs error corrections ("EC") of "ECC blocks"
(16 sectors). The ECC unit writes error location and correction data to the MCU. The MCU
reads the erroneous data words from the SDRAM, correct them and writes the corrected words
back to the SDRAM. The number of EC passes (on rows and columns alternating) is adaptive.
EC "statistics" can be read by the CPU for "re-try" or other error handling and track buffer
management decisions.
Detection) function was performed, the EDC error indication is added at the end of the
sector data replacing the original 4 EDC bytes. For DVD discs, the ECC unit reads media data
from the SDRAM through the MCU and performs error corrections ("EC") of "ECC blocks"
(16 sectors). The ECC unit writes error location and correction data to the MCU. The MCU
reads the erroneous data words from the SDRAM, correct them and writes the corrected words
back to the SDRAM. The number of EC passes (on rows and columns alternating) is adaptive.
EC "statistics" can be read by the CPU for "re-try" or other error handling and track buffer
management decisions.
2.5 SERVO - Servo Signal Processing Unit
The SERVO unit receive up to 8 analog signals from the RF amp device through the AFE after
external low pass filtering. The signals are converted to digital and transferred to a dedicated
programmable 16 bits DSP that perform the needed calculations for servo loop closing, closed
loop maintenance and reclosing when a loop is inadvertently opened. In addition to the analog
signals the SERVO unit receives DPLL rate and lock and defect indication from the DRC unit.
The servo loops handled are:
external low pass filtering. The signals are converted to digital and transferred to a dedicated
programmable 16 bits DSP that perform the needed calculations for servo loop closing, closed
loop maintenance and reclosing when a loop is inadvertently opened. In addition to the analog
signals the SERVO unit receives DPLL rate and lock and defect indication from the DRC unit.
The servo loops handled are:
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Focus – Find and maintain focus
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Spindle - Change and maintain speed to achieve constant linear velocity or bit-rate while the
radius is increasing along the spiral track
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Sled - Rough radial position tracking and maintenance along the spiral track
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Tracking - Fine radial position tracking and maintenance
The SERVO unit also contains two 11 bits DACs, and 9 PWMs of the high frequency
“uniform” type. The regular PWM circuits output can be used (through an external RC filter
and servo amplifier device) to feed the spindle and sled motors of the loader.
The second task of the SERVO unit is to perform, under DSP control, fast and accurate jumps
to a given track of the disc or to the BCA position (for DVD discs) across the spiral track, or to
change layers for two layers DVD discs.
The third task of the SERVO unit is to identify the disc type.
“uniform” type. The regular PWM circuits output can be used (through an external RC filter
and servo amplifier device) to feed the spindle and sled motors of the loader.
The second task of the SERVO unit is to perform, under DSP control, fast and accurate jumps
to a given track of the disc or to the BCA position (for DVD discs) across the spiral track, or to
change layers for two layers DVD discs.
The third task of the SERVO unit is to identify the disc type.
2.6 DSP - Digital Signal Processor
The 16 bits DSP has internal instruction and data RAMs. DSP SW is down loaded from the
NOR Flash external memory by the CPU. The DSP can overlay SW “pages” from the SDRAM
using a DMA facility.
NOR Flash external memory by the CPU. The DSP can overlay SW “pages” from the SDRAM
using a DMA facility.
2.7 CPU - Central Processing Unit
The CPU is the central processing unit of the Vaddis 778. It is based on a 16 bits Intel 186
instruction set compatible licensed CPU core. The CPU executes from a NOR type Flash
memory with 16 bit data bus. Alternately, a compatible EPROM, PROM, OTPROM or masked
ROM can be connected.
The CPU core has attached to it 2 Kwords instruction cache, 4 KWords instruction ROM, 10
KWords "scratch pad" data/instruction RAM and peripheral units mentioned below.
The peripherals are the CPU_Bus Interface (CBI), External PNVM/SRAM interface (XMI),
Front panel concentrator interface (SSC) and MCU interface unit (MIF). Another (external to
the CPU) peripheral is the BE/CPU interface (BCI).
The core has internal real-time clock unit, two UART units, GPIO control unit and interrupt
handler.
Most of the data transferred over the CPU_Bus are called CPU parameters. The CPU SW
always writes and reads 16 bits (or multiple of 16 bits transferred consecutively to/from the
same CPU_Bus address) for each parameter. CPU parameters written or read from the same
instruction set compatible licensed CPU core. The CPU executes from a NOR type Flash
memory with 16 bit data bus. Alternately, a compatible EPROM, PROM, OTPROM or masked
ROM can be connected.
The CPU core has attached to it 2 Kwords instruction cache, 4 KWords instruction ROM, 10
KWords "scratch pad" data/instruction RAM and peripheral units mentioned below.
The peripherals are the CPU_Bus Interface (CBI), External PNVM/SRAM interface (XMI),
Front panel concentrator interface (SSC) and MCU interface unit (MIF). Another (external to
the CPU) peripheral is the BE/CPU interface (BCI).
The core has internal real-time clock unit, two UART units, GPIO control unit and interrupt
handler.
Most of the data transferred over the CPU_Bus are called CPU parameters. The CPU SW
always writes and reads 16 bits (or multiple of 16 bits transferred consecutively to/from the
same CPU_Bus address) for each parameter. CPU parameters written or read from the same
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