DV-660H (serv.man2). start to section 13-4 - Sharp DVD Service Manual (repair manual). Page 44

AUDATA1—Digital Audio Output 1: Pin 40

PCM multiformat digital-audio data output, capable of only two-channel 20-bit output. This PCM output defaults to VSS as output until
enabled by the DSP software.

AUDATA0—Digital Audio Output 0: Pin 41

PCM multiformat digital-audio data output, capable of two-, four-, or six-channel 20-bit output. This PCM output defaults to VSS as output
until enabled by the DSP software.

MCLK—Audio Master Clock: Pin 44

Bidirectional master audio clock. In audio master timing mode, MCLK is an output from the CS4923 that provides an oversampled audio-
output clock at either 128 Fs, or 256 Fs, 512 Fs. MCLK is used by the output formatter and the XMT958 digital transmitter port. In slave
mode, the user can input MCLK at 128 Fs, 256Fs, 384Fs, or 512 Fs, which then can be used to sequence the digital-audio output interface,
including the division and output of SCLK and LRCLK.

SCLK—Audio Output Bit Clock: Pin 43

Bidirectional digital-audio output bit clock. In output master timing mode or MCLK slave mode, SCLK is an output that is divided from MCLK
to provide 32 Fs, 64 Fs,128Fs, 256 Fs, or 512 Fs, depending on the MCLK rate and the digital-output configuration. In total slave mode,
SCLK is an input and can be any common bit clock rate. In total slave mode, SCLK is totally independent of MCLK. SCLK defaults to an
input upon reset.

LRCLK—Audio Output Sample Rate Clock: Pin 42

Bidirectional digital-audio output-sample-rate clock that is always synchronous with SCLK. In output master timing mode or MCLK slave
mode, LRCLK is an output that is divided from MCLK to provide the output sample rate depending on the output configuration. In total slave
mode, LRCLK is an input and can be totally asynchronous to the other clocks, including MCLK. LRCLK defaults to an input upon RESET low.

XMT958—SPDIF Transmitter Output: Pin 3

Logic-level output that contains a biphase-encoded clock for synchronously outputting two channels of PCM digital audio or a Dolby Digital
compressed-data interface or both. This output typically connects to the input of an RS-422 transmitter or to the input of an optical
transmitter.

SCLKN1, STCCLK2—PCM Audio Input Bit Clock: Pin 25

Bidirectional digital-audio PCM bit clock that is an output in master mode and an input in slave mode. SCLKN1 defaults to an input upon
RESET low. In slave mode, SCLKN1 can operate totally asynchronous from the CS4923 clock generator. In master mode, SCLKN1 is
derived from the CS4923 internal clock generator.In either master or slave mode, the active edge of SCLKN1 can be programmed by
the DSP. For applications supporting MPEG playback where a system time clock(STC) is required to support audio/video syschronization
and CLKIN is no driven with a 27-MHz clock, this pin functions as STCCLK2, which provides a path for connection the 27-MHz time-base
clock directly to the internal STC counter.

LRCLKN1—PCM Audio Input Sample Rate Clock: Pin 26

Bidirectional digital-audio PCM  input sample-rate clock that is an output in master mode and an input in slave mode. LRCLKN1 defaults
to an input upon RESET low. LRCLKN1 delineates audio subframes. LRCLKN1 is derived from the CS4923 internal clock generator for
master mode. In slave mode,  LRCLKN1 can operate totally asynchronously from the CS4923 clock generator. In either master or slave
mode,  LRCLKN1 can be sampled with either edge of SCLKN1, depending on the SCLKN1 active-edge configuration.

SDATAN1—PCM Audio Data Input Number One: Pin 22

Multiformat/multichannel digital-audio PCM data input that can input from one to six channels of PCM, as well as inputting compressed
data. SDATAN1 can be sampled with either edge of SCLKN1, depending on the SCLKN1 configuration. Data format for SDATAN1 is
programmable.

CMPCLK, SCLKN2—PCM Audio Input Bit Clock: Pin 28

Bidirectional digital-audio PCM  bit clock or compressed-data clock that is an output in master mode and an input in slave mode. SCLKN2
defaults to an input upon RESET low. In slave mode, SCLKN2 can operate totally asynchronously from the CS4923 clock generator. In
master mode, SCLKN2 is derived from the CS4923 internal clock generator. In either master or slave mode, the sctive edge of SCLKN2
can be programmed by the DSP.If this pin is configured as CMPCLK, then it is used to clock CMPDAT into the CS4923 input buffer.

CMPREQ, LRCLKN—PCM Audio Input Sample Rate Clock: Pin 29

Bidirectional multimode signal that can be used as a programmable-polarity compressed-data-request output signal (CMPREQ) in the
serial compressed data input mode or the parallel host compressed data mode. If it is used for a digital-audio interface, LRCLKN2 functions
as a bidirectional digital-audio PCM bit clock that is an output in master mode and an input in slave mode. LRCLKN2, CMPREQ defaults
to an input upon RESET low. In slave digital audio mode, LRCLKN2 can operate totally asynchronously from the CS4923 clock generator.
In master mode, LRCLKN2 is derived from the CS4923 internal clock generator. In either master or slave mode, LRCLKN2 can be sampled
with either edge of SCLKN2 depending on the SCLKN2 configuration.

CMPDAT, RCV958, SDATAN2—PCM Audio Data Input Number Two: Pin 27

Multiformat/multichannel digital-audio PCM data input that can input from one to six channels of PCM as well as inputting compressed
data. SDATAN2 can be sampled with either edge of SCLKN2 depending on the SCLKN2 configuration. SDATAN2 input can be
programmed to be flush left or flush right. If configured for RCV958 mode, this pin provides an input for IEC6-958/61937, accepying
biphase-encoded compressed data or PCM or both. If the RCV958 input is used to recover data, then the CS4923 clock manager is slaved
to the 64 Fs sample-rate clock recovered from the input.

DC—Reserved: Pin 38

This pin is reserved and should be pulled up with an external 10k resistor.

DD—Reserved: Pin 37

This pin is reserved and should be pulled up with an external 10k resistor.