DV-660H (serv.man2). start to section 13-4 - Sharp DVD Service Manual (repair manual). Page 43

VDDA—Analog Positive Supply: Pin 34

Analog positive supply for clock generator. Nominally +3.3 V.

VSSA—Analog Supply Ground: Pin 35

Analog ground for clock generator PLL.

VDD1, VDD2, VDD3—Digital Positive Supply: Pins 1, 12, 23

Digital positive supplies. Nominally +3.3 V.

VSS1, VSS2, VSS3—Digital Supply Ground: Pin 2, 13, 24

Digital ground.

FILTS—Phase-Locked Loop Filter Cap Positive: Pin 33

Connects to an external filter capacitor for the on-chip phase-locked loop.

FILTD—Phase Locked Loop Filter Cap Negative: Pin 32

Connects to an external filter capacitor for the on-chip phase-locked loop.

CLKIN—Master Clock Input: Pin 30

Connects to the input of the clock manager PLL. The DSP clock is connected to the PLL output when the CLKSEL pin is set low. When
CLKSEL is high, CLKIN directly connects to the internal DSP clock.

CLKSEL—DSP Clock Select: Pin 31

CLKSEL low selects the clock-manager PLL output as the DSP clock. CLKSEL high selects CLKIN directly from the input as the internal
DSP clock.

DATA7 (or EMAD7 or GPIO7) — Pin8
DATA6 (or EMAD6 or GPIO6) — Pin9
DATA5 (or EMAD5 or GPIO5) — Pin10
DATA4 (or EMAD4 or GPIO4) — Pin11
DATA3 (or EMAD3 or GPIO3) — Pin14
DATA2 (or EMAD2 or GPIO2) — Pin15
DATA1 (or EMAD1 or GPIO1) — Pin16
DATA0 (or EMAD0 or GPIO0) — Pin17

In parallel host mode, these pins provide bidirectional operation. If a serial host mode is selected, these pins can provide a multiplexed
address and data function for connecting an 8-bit external memory. Otherwise, in serial host mode, these pins can act as general-purpose
input or output pins that can be individually configured and controlled by the internal DSP.

A0, SCCLK—Host Parallel Address Bit Zero or Serial Control Port Clock: Pin 7

In parallel host mode, this pin serves as an address input pin to help select one of four parallel registers. In serial host mode, this pin serves
as the serial data clock signal, specifically as the SPI clock input or the I

2

C clock input.

A1, SCDIN—Host Address Bit One or SPI Serial Control Data Input: Pin 6

In parallel host mode, this pin seves as an address input pin to help select one of four parallel registers. In SPI serial host mode, this pin
serves as the data input.

RD, R/W, EMOE, GPIO11—Host Parallel Output Enable or Host Parallel R/W or External Memory Output Enable or General Purpose

Input & Output Number 11: Pin 5

In Intel parallel host mode, this pin serves as the active-low data-bus-enable input. In Motorola parallel host mode, this pin serves as the
read-high, write-low input signal. In serial host mode, this pin serves as the external memory active-low data-enable output signal. Also
in serial host mode, this pin acts as a DSP-addressable-control-register-external input or output bit.

WR, DS, EMWR, GPIO10—Host Write Strobe or Host Data Strobe or External Memory Write Enable or General Purpose Input &

Output Number 10: Pin 4

In Intel parallel host mode, this pin serves as the active-low data-write-input strobe. In Motorola parallel host mode, this pin serves as the
active-low data-strobe-input signal. In serial host mode, this pin serves as the external-memory active-low write-enable output signal. Also
in serial host mode, this pin acts as a DSP-addressable-control-register-external input or output bit.

CS—Host Parallel Chip Select, Host Serial SPI Chip Select: Pin 18

In parallel host mode, this pin seves as the active-low chip-select input signal. In serial host SPI mode, this pin is used as the active-low
chip-select input signal.

RESET—Master Reset Input: Pin 36

Asynchronous active-low master-reset input. Reset should be low at power-up to initialize the CS4923 and to guarantee that the device
is not active during initial power-on stabilization periods. Reset can also reinitialize the CS4923 during normal operation with nominal
supply voltages. Reset also initializes and selects the host interface and initiates an automatic boot cycle if serial host mode is selected
and ABOOT is low. Reset being low disables the outputs of all the bidirectional pins, forcing them into a high-Z input mode.

SCDIO, SCDOUT, PSEL, GPIO9—Serial Control Port Data Input and Output, Parallel Port Type Select: Pin 19

In serial control port mode, this pin serves as the open-drain bidirectional data pin for the I

2

C serial host control port or the data output

pin for the SPI serial host control port. In parallel host mode, this pin is sampled at the rising edge of RESET to configure the parallel host
mode as an Intel type bus or as a Motorola type bus.In paralle host mode, after the bus mode has been selected, the pin can function as
a general-purpose input or output pin that is uniquely.

EXTMEM, GPIO8—External Memory Chip Select or General Purpose Input & Output Number 8: Pin 21

In serial control port mode, this pin acts as an output to provide an independent chip-select capability to connect external byte-wide RAM
or ROM. In parallel and serial host mode, this pin can also function as a general-purpose input or output pin that is uniquely addressable
by the DSP.

INTREQ, ABOOT—Control Port Interrupt Request, Automatic Boot Enable: Pin 20

Open-drain control-port interrupt-request output that is addressable by the DSP. In serial port mode, this pin functions as a request line
prompting further cummunication or for initiating dialog between the host and the DSP.Also in serial host mode, this signal initiates an
automatic boot cycle from external memory if it is held low as the CS4923 transitions from a reset state.

AUDATA2—Digital Audio Output 2: Pin 39

PCM multiformat digital-audio data output, capable of only two-channel 20-bit output. This PCM output defaults to VSS as output until
enabled by the DSP software.