Read Panasonic KX-NS5170XSX / KX-NS5170X-SX Service Manual online
7
KX-NS5170X/KX-NS5170SX
5.2.
Hardware Functional Specification
5.2.1.
Control-System Circuit
5.2.1.1.
DLC FPGA
5.2.1.2.
TACKER ASIC
• Local TSW
Exchanges the time slots between CT bus (1024ch) and local highway (64ch).
Function
Specifications
FPGA Internal Processer
NiosII CPU
Interface
CPU Board I/F
Bus Timing
TI CortexA8 CPU Bus Interface
Data Bus
8bit
Address Bus
11bit
Interrupt Control
External Interrupt
Up to 2
Internal Interrupt
Up to 3
SLIC Control
Number of SLIC
Up to 2
DPT Control
Delay Measurement
16bit with data latch
SLC
MPR_BUS
DLC_FPGA
DLC_FPGA
SPI
CPU
CPU
CS_DLY
FH
P23
INT
SLIC_INT
DPRAM
INT_CON
Local
Bus
Local
TSW
Host
Local- bus I/F
DPLL
JTAG
GAIN
Internal Highway
Internal bus
APITS
controller
HDLC
8ch
FIFO /
DPRAM
DPITS
controller
Highway
Local
Highway I/F
PT-I/F
PITS
D
GPIO-i/f
GPIO
CODEC
controller
RT_SND
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