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6
KX-NS5170X/KX-NS5170SX
5 Technical Descriptions
5.1.
Block Diagram
DHL
C
4
Block
Diagram
DPT
I/F
Dr
iv
er
&
Rec
ei
v
e
r
Se
rg
e
EMC
DTB
0
Pul
s
e
Tr
a
n
s
Po
w
e
r SE
L
Ov
er
lo
a
d
Pr
ot
ec
ti
on
PT
_
P
OW
0
DTA
0
PT
_
C
U
R
0
Port #3
(Sam
e
as
Port #1)
D1A
D2A
Por
t #1
D1C
D2C
DR
0
+4
0
V
+3
.3
V
VR
EF
VREF
+
TAC
KER
ASIC
DLC
FPGA
EP4
C
E
1
0
NI
OS
P4
[0
]
P5
[0
]
RX
[0
]
TXA[
0
]
TXB[
0
]
FLASH
ROM
8M
B
it
SR
AM
1M
B
it
A_
T
[1
2
:0
]
A[
1
9
:1
]
A[
1
6
:0
]
A
[12:0]
D_T
[7:0]
D[15:0]
D[7:0]
D[7:0]
nW
R
_
T
nRD_T
nW
R
nRD
nW
R
nRD
nW
R
nRD
nCS
_D
M
A
nC
S
_
D
M
A
nCS
nCS
_D
M
A
SR
AM
1M
B
it
A[
1
6
:0
]
D[7:0]
nW
R
nRD
nCS
nCS
0
nCS
I
nCS
0
nCS
1
nCS
20
nCS
21
nCS
20
nCS
21
nRE
S
E
T
0_M
nRE
S
E
T
nRE
S
E
T
0_M
nW
A
IT
nW
A
IT
nB
A
C
K
nB
R
E
Q
nB
A
C
K
nB
R
E
Q
nA
L
E
nA
L
E
XT
AL
16.384
MH
z
nIRQ1
nIRQ0
P
LLCLK
ECCL
K
P2
3
DELA
Y0
DEL
A
Y
0
CP[7:0]
CP
[7:0]
LDH
W
LUH
W
0
LUH
W
0
LDH
W
0
nC
ON
FIG
HW
C
L
K
2
_
M
HW
C
L
K
_
M
HW
F
H
2
_
M
HW
F
H
_
M
LDH
W
2_M
LUH
W
2_M
LDH
W
_
M
LUH
W
_
M
A_
M
[9
:0
]
D_M
[7:0]
nW
A
IT
_
M
nW
A
IT
D[7:0]
A
[9:0]
n
RD_
M
n
RD_
M
nW
R
_
M
nW
R
_
M
nC
S
_
M
nC
S
0
_
M
nC
S
1
_
M
nI
N
T
_
M
nI
N
T
0
_
M
n
INT
1_M
IRQ2
B
E
LL_S
Y
N
C
IRQ0
HAL
T
IRQ3
ACAL
M
nR
E
S
E
T
1
_
M
HW
C
L
K
3
_
M
H
W
_F
H3_M
TO
und
er
boar
d
TO
upp
er
boar
d
nCS
nRE
S
E
T
Har
d
Revi
si
on
CA
R
D
ID[7:0]
+
40V
+
3.3V
n
R
ES
ET
0
_
M
SH
W
_
CL
K
SH
W
_
F
H
SH
W
F
H
SH
W
C
L
K
LUH
W
0
LUH
W
0
LDH
W
LD
H
W
TM
S
TC
K
TD
I
TD
O
Debug
JT
A
G
Port
S
i3226
1
nC_CS
[0]
C_INT
[0]
40V
Se
rg
e
EM
C
DCDC
40V
DCDC
Se
rg
e
EM
C
SL
IC
/C
O
D
EC
2c
h
C_DOUT
nS
L
C
R
S
T
TA
RA
TB
RB
LD
H
W
LU
H
W
1
HW
F
H
HW
C
L
K
C_DIN
C_DC
LK
SPI
0
PCM
H
W
SLT
I/F
SLT
I/F
+1
5
V
DHLC
DPT
I/F
Dr
iv
er
&
Rec
ei
v
e
r
Se
rg
e
EMC
DTB
1
Pul
s
e
Tr
a
n
s
Po
w
e
r SE
L
Ov
er
lo
a
d
Pr
ot
ec
ti
on
PT
_
P
OW
1
DTA
1
PT
_
C
U
R
1
D1B
D2B
DR
1
+4
0
V
+1
5
V
Por
t #2
DHLC
TC
RC
Port #4
(Sam
e
as
Port #
2
)
D1D
D2D
TD
RD
PT
C
T
R
PT
CTR
nC_CS
[1:0]
C_
DOUT
C_DIN
C_
DC
L
K
nS
L
C
R
S
T
(I
/O
)
C_INT
[0]
VREF
-
VREF
C
Ov
e
r
Vo
lt
age
Pro
te
ct
io
n
DC/
DC
+1
5
V
POR
T1
-2
POR
T3
-4
XT
AL
25M
H
z
CAR
D
ID
CLK
CA
R
D
ID[3:0](
I/
O)
Se
ri
a
l
RO
M
for Confi
g
4M
bi
t
DAT
A
DCLK
nC
S
O
DAT
A
DCLK
nCS
ASDO
ASDI
C_INT
[1]
IRQ6
IRQ7
nW
R
_
L
nRD_L
D_L[15:0]
A_
L
[1
9
:0
]
DC/
DC
+2
.5
V
+1
.2
V
P2
4
SH
W
C
L
K
SH
W
F
H
HW
C
L
K
HW
F
H
LUH
W
1
LUH
W
1
+5
V
DC/
DC
A
_L[19:1]
A
_L[16:0]
A
_
L[16:0]
D_L[15:0]
D_L[7:0]
D_L[7:0]
nW
R
_
L
nW
R
_
L
nW
R
_
L
nRD_L
nRD_L
nRD_L
nW
R
_
L
nRD_L
A_
L
[1
9
:0
]
D_L[15:0]
HW
F
H
HW
C
L
K
0
HW
F
H
HW
C
L
K
KX-NS5170X/SX BLOCK DIAGRAM
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