KX-NS0130X - Panasonic PBX Service Manual (repair manual). Page 5

5

Functional Block 

Functional contents

Communication highway between shelves

It connects PCM highways among NS1000 main card, Legacy GW#1  and Legacy GW#2.
It wires them in a star shape configuration centering the TSW in FPGA on the STACK-M mounted on 
NS1000.
Allocation between TSW shelves of 1024ch X 1024ch in capacity (physical channel number) is as 
follows:
Basic shelf 384ch
Legacy GW#1 384ch
Legacy GW#2 384ch
Highway 8MHz X 9stream, 3stream for each Legacy GW.
It operates in a fixed delay mode which ensures isochronous frames.
A inter-shelf highway clock (SHW_CLK) and frame header (SHW_FH) which are synchronized with 
the Internal Highway in NS1000 are generated in FPGA on STACK-M card.
SHW_CLK and SHW_FH are delivered to the STACK-S card in the Legacy GW's.

Clock distribution and selection based on the 
network

Distribution of clock based on the network
It drives the NETREF to Main FPGA by selecting line synchronization signal (one input for each 
shelf) from the Legacy GW on the STACK-M card.

Intersystem Communication Controller

It has a CircLink (TMC20073) chip as a inter-shelf communication controller
On the STACK-M card there are 2 Circlink chips for Legacy GW#1 and #2.and it connects  by one to 
one bitween STACK-M and STACK-S.

CPU Interface

From CPU on Main card, register access is performed to the device (FPGA, Circlink) on STACK-M. 

Interruption

It relays the STACK interruptions, which are triggered by a CircLink #1 or #2 or detection of connect 
(or disconnect) of the Legacy GW #1 and #2, to the Main CPU.
Equipped with interruption factor registers and enable registers

Operation and MaintenanceFault Detection 
Function

Connect and disconnect detection of expansion shelf # 1
Connect and disconnect detection of expansion shelf # 2
It delivers RING_SYNC of a basic shelf to Legacy GW # 1 and # 2.
Display function of status notification port of expansion shelf # 1 and #2 within 2bits.
It delivers connect signal of each shelf and shelf number to expansion shelf # 1, # 2, and # 3.

Reset Control

It relays Main card system reset signal
Reset signal generation according to each Legacy GW.

LED contorl circuit

There are two green LED to indicate connection state with each Legacy GWs to the front panel.

Connector for Main Card

Connection for NS1000 Main card.(120pin)
CPU local bus, PCM Highway, Card ID.

Connector for Legacy GW

The two connectors for stacking cables (50 pins) is installed on the front panel. 

FPGA Configuration

FPGA on STACK-M card starts a configuration by software control. 
The Main CPU detects that the configuration was completed using the port information from STACK-
M, and resets release and starting processing. 

Power suply circuit

Input : +15V
Output: +3.3V(DC-DC converter), For FPGA:+1.2V(Series Reg.)