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8.4. PROCESS BLOCK DIAGRAM
3
72
6
74
25
27
29
30
70
71
67
68
MNA1
MNA4
MNA5
MNA5
MNA7
MND0
MND2
MND5
MND15
IC5001
7
17
22
21
MND3
MND4
12
22
13
21
15
19
14
20
11
23
10
24
17
17
16
18
CN301 CN3
45
41
50
49
48
47
42
46
SD CLK
SDO CMD
SDO CD
SDO WD
IC4001
69
65
36
60
21
22
70
84
XSTANDBY
XMNCS
MNIRQ
MNII
XMNRE
XMNWE
SD STBY
SD CS
SD IRQ
SD IRQ2
OE
WE
79 MCLK
MNCLK
DBE CLK
35
XRST
MCU RST
67 WAIT
IC3001 MCU WAIT
30
29
5
SCK1
SO1
LCD SEN
To LCD(IC7501)
102
109 111
118 120 1
3
85
100
IC4002
(8Mbit_FLASH MEMORY)
79
72
71
70
67
35
82
81
59
17
MCLK
DBE WRHN
DBE WRLN
OE
MCU WAIT
MCU RST
MCU CLK
MCU WRH
MCU WRL
MCU RD
MCU WAIT
DBE RESET
DYN SW
DBE CLK
(IC5001 67 )
(IC5001 67 )
DBE ASN
DBE CS
DBE IRQ
BCLKOUT
DBE AS
DBE CS
DBE IRQ
MCU D16~D31(DATA)
MCU A0~A15(ADDRESS)
MCU A01~A07(ADDRESS)
MCU
D16~D31(DA
T
A
)
MCU A16~A19(ADDRESS)
3
4
2
(27MHz)
REG3.1
X3001
VCLK
3
4
2
(48MHz)
REG3.1
X3002
USB
2
1
5
6
IC3002
AFE CLK
IC1001
(AFE IC)
AFE D0~D11(PRE VIDEO SIGNAL)
CCD
1
1
2
2
3
3
4
4
5
5
7
7
8
8
10
10
11
11
13
13
CN4 CN201
32
31
TXD
RXD
3
5
3
IC4003
5
2
6
1
IC4004
33
PRXDEN
19
PRXSDRQ
2
7
1
IC4005
76
68
DDIVCC
INITX
63
JACK CTL
39
38
27
26
IIC SCL
IIC SDA
IC4501
IIC SCL
IIC SDA
USB ON 29
REG3.1
REG4.9
22
USB SEL
Q3003
2
3
4
5
6
11
10
OE
RCV
VP
VM
SUSPND
IC3301
CPU
I/F
VCLK
USB 4XCLK
AFE
I/F
AFE CLK
AFE SOF/AFE VPIX
SDRAM I/F
43
59
44
45
30
29
14
28
13
27
58
12
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
40
55
54
56
25
RAS
CAS
WE
CS
CLK
47 48 49 34 50 51 52 7 6 5 19 4 3 2 16
D01
D02
D03
D04
D05
D06
D07
D08
D09
D010
D01
1
D012
D013
D014
D015
SD-RAM
(64M)
ADDRESS
CONTROL SIGNAL
IC3501
(64M SDRAM)
DATA (D01~D015)
CONTROL SIGNALS
MA0~11(ADDRESS)
USB
I/F
IC3001
REG3.1
REG3.1
Q3001
Q3002
7
27
8
26
5
29
13
21
14
20
16
18
CN3 CN301
Y+(G)
Cr+(R)
Cb+(B)
1
2
4
IC101
FROM IC4001
LCD
I/F
46
47
48
39
40
38
LCD R
LCD G
LCD B
CLK
DI
CS
IC7501
24
22
20
R OUT
G OUT
B OUT
22
23
24
LCD
IC7502
REG17.5
J7701
J7702
Q7702
LCD BACK LIGHT
USB TERMINAL
J203
J203
3
4
2
1
V OUT
J202
J202
5
IC201
4
3
4 5
6
7
8
3
2
1
SERIAL
MCU
A16
MCU
A00
MCU
A07
MCU
A08
MCU
A15
MCU
A17
MCU
A19
MCU
D16
MCU
D31
USB SENS
USB D-
USB D+
JACK CTL
VOUT
TXD
RXD
PR XDEN
PR XSDRQ
P JUDGE
SDO DAT0
SDO DAT1
SDO DAT2
SDO DAT3
SD
CARD
DRIVE
CARD
DRIVE
D+
D-
Pin1
Pin2
Pin3
COMP+
IC1501
1
2
4
30
REG3.1
Q7701
(SD_IF)
(MAIN CPU)
187
59
124
58
123
8
142
130
60
125
4
79
239
134,70
(DBE)
73
193
74
194
(SUB CPU)
(LCD VIDEO INTERFACE)
(LCD TIMING CONTROLLER)
PROCESS BLOCK DIAGRAM
DMC-F7PP/E/B/A/EN PROCESS BLOCK DIAGRAM
DMC-F7PP / DMC-F7E / DMC-F7E1 / DMC-F7B / DMC-F7B1 / DMC-F7A / DMC-F7EN
14
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