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8.2. SYSCON (COMMUNICATION) BLOCK DIAGRAM
REG3.1
REG4.9
Q3003
23
33
32
31
30
IC1501
TGADCLK
TG CS
SCK1
SOK1
MCK
IC1201
22
MCK
IC3001
IC3501
25
56
54
55
40
MCLK
MCS
MWE
CAS
RAS
MCLK 0
MCLK 1
MCS
MWE
CAS
RAS
DBE CLK
DBE IRQ
DBE CS
DBE AS
DBE RESET
MCU WRL
MCU WRH
MCU RD
MCU CLK
MCU WAIT
AFE CLK
CLK 27M
USB D+
USB D-
27
6
3
IC1001
(AFE)
ADC CLK
AFE IRQ
AFE CS
SER SCLK
SER SD
3
2
X3001
(27MHZ)
4
20
6
IC4001
30
27
26
25
28
29
2
1
74
76
73
39
38
23
24
25
27
26
SC1
SC0
SO0
SI0
SI1
SO1
TG_CS
AFE_IRQ
AFE_CS
STB CPU
RST CPU
INT CPU
IIC SCL
IIC SDA
STB CPU
RST CPU
INT CPU
IIC SCL
IIC SDA
28
10
11
10
5
6
3
4
2
IC3301
USB D+
USB D-
USB TERMINAL
J203
J203
29
37
4
31
OE
RCV
VP
VM
SUSPND
USB ON
USB SEL
22
FL RST
RESET
IC4501
5
21
22
36
60
79
17
59
81
35
71
72
67
70
84
58
71
70
68
OE
WE
FL CE
IC4002
OE
WE
FL CE
LCD SEN
SQ IRQ
SD IRQ2
SD STBY
SD CS
M CLK
DBE IRQ
DBE CS
DBE ASN
MCU RST
DBE WRLN
DBE WRHN
WAIT
67
69
65
30
29
IC5001
MNIRQ
MNIRQ2
XSTANDBY
XMNCS
MNCLK
XRST
XMNRE
XMNWE
39
40
38
CN3
IC7501
41
42
45
46
50
49
48
47
CLK
DI
CS
SCKO
SPICD
SO0
SI0
SPICS
(IC4001
)
(IC4001
)
69
SD CLK
SDO CD
SDO CMD
SDO WP
SDO DAT0
SDO DAT1
SDO DAT2
SDO DAT3
: ADRESS/DATA LINE
SCK1
SCK0
SO0
SI0
SI1
SO1
CN3 CN301
CN301
SD
CARD
DRIVE
CARD
DRIVE
22
12
17
17
21
13
18
16
19
15
20
14
23
11
24
10
8
16
18
13
21
14
20
CN201 CN4
1
1
2
2
3
3
1 2
4 3
To IC3001
LCD
(SUB CPU)
(8Mbit_FLASH
MEMORY)
(MAIN CPU)
123
187
58
59
124
8
130
60
125
142
141
78
44
111
221
42
41
219
239
4
(DBE)
(64M_SDRAM)
(SD_IF)
(LCD VIDEO INTERFACE)
SYSCON (COMMUNICATION) BLOCK DIAGRAM
DMC-F7PP/E/B/A/EN SYSCON (COMMUNICATION) BLOCK DIAGRAM
(T.G)
DMC-F7PP / DMC-F7E / DMC-F7E1 / DMC-F7B / DMC-F7B1 / DMC-F7A / DMC-F7EN
12
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