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11
BB-HCM547CE
4.2.
Camera Block (Image signal processing, LENS control)
[VIDEO Board]
• IC201 is a MOS type image sensor of approximately 370 thousand pixels, which outputs the image signal (M_OUT) of an VGA
(640x480) size.
• IC202: This IC is to remove noise in the M_OUT signal, adjust the gain and output the 12-bit data (D_OUT[11:0]).
IC202 includes TG (Timing Generator) generation function of the MOS image sensor (IC201), synchronizing signals genera-
tion function (PCLK, VD and HD), noise removal (CDS: correlative double sampling) function of image signal (M_OUT) and
12-bits A/D conversion function.
The pixel clock (PCLK), synchronizing signal (VD and HD) and 12-bit data (D_OUT [11:0]) that are output from the IC202 are
input into the LVDS Transmitter IC on IC203, and after being parallel-serial converted, they are converted into the two-wire
differential signals. Then the signals are transmitted to the LVDS Receiver IC (IC604) on the Main board. In the LVDS
Receiver IC (IC604), the signals are then serial-parallel converted to recover the pixel clock and the 12-bit data, which are
output to the CPU (IC101). (Refer to Fig. 1.)
tion function (PCLK, VD and HD), noise removal (CDS: correlative double sampling) function of image signal (M_OUT) and
12-bits A/D conversion function.
The pixel clock (PCLK), synchronizing signal (VD and HD) and 12-bit data (D_OUT [11:0]) that are output from the IC202 are
input into the LVDS Transmitter IC on IC203, and after being parallel-serial converted, they are converted into the two-wire
differential signals. Then the signals are transmitted to the LVDS Receiver IC (IC604) on the Main board. In the LVDS
Receiver IC (IC604), the signals are then serial-parallel converted to recover the pixel clock and the 12-bit data, which are
output to the CPU (IC101). (Refer to Fig. 1.)
• Oscillation frequency of the IC202 is 17.172MHz and the clock signal is generated with the use of the crystal oscillator (X201).
• The IC202 is controlled by the serial signals (CS_AFE, SDI, and SCL) in the CPU (IC101).
• The IC202 is controlled by the serial signals (CS_AFE, SDI, and SCL) in the CPU (IC101).
The SDI and SCL signals in the serial signals are shared and used in the DA converter (IC903) mounted on the LENS board.
(Refer to Fig. 2.)
(Refer to Fig. 2.)
• Hard reset (RESET) of IC202 is controlled by GPIO of IC101 on the Main board.
• The power supplies used in the camera block are made +5.6V into +5.0V by the IC206 and are made +5.0V into +3.1V by the
• The power supplies used in the camera block are made +5.6V into +5.0V by the IC206 and are made +5.0V into +3.1V by the
IC204 supplied from the main board.
Figure 1 Video Signal Transmission via LVDS
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