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BB-HCM547CE
Figure 2 Sharing of Serial Signals (SDI and SCL)
[Main Board]
• Pixel clock (PCLK: 17.172MHz), 12-bit RAW (AFE_D[11:0]) and synchronizing signal (AFE_VD and AFE_HD) that are output
from the IC202 are transmitted to the LVDS Receiver IC (IC604) on the Main board via the LVDS Transmitter. They are serial-
parallel converted in the LVDS Receiver IC (IC604) and are output recovered the pixel clock (CCDCLK), 12-bit RAW data (CCD
[11:0]) and synchronizing signal (CCDCLK and CCDHD) into the CPU (IC101).
parallel converted in the LVDS Receiver IC (IC604) and are output recovered the pixel clock (CCDCLK), 12-bit RAW data (CCD
[11:0]) and synchronizing signal (CCDCLK and CCDHD) into the CPU (IC101).
• In the VIDEO SIGNAL Processor block incorporated in IC101, the RAW data is subjected to such signal processing as OB
clamping, white balancing, and
γ
processing, then the RAW data is temporary recorded in the external SDRAM. The RAW data
is subjected to the three-step processing that is composed of pixel correction, YC generation and scaling, and the data after the
processing is recorded in the same external SDRAM as the image data.
processing is recorded in the same external SDRAM as the image data.
• The serial control signals (SDI, SCL and CS_AFE) from the CPU (IC101) on the main board are sent to the AFE/TG IC (IC202)
on the VIDEO board via CN651.
[LENS Board]
Camera has 2.3 X optical zoom lens. This lens unit has the ZOOM lens drive motor and the IRIS unit. These components are
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