Read LG 47LEX8-ZA (CHASSIS:LD03S) Service Manual online
2V5
2K
R11477
100
R11443
TB2-
TDO_FPGA
100
R11424
22
R11451
SYSCLK
2V5
TA8-
DATA0
FDV301N
Q11400
G
D
S
0 . 1 u F
16V
16V
C11400
LVTX1_CLK+
2V5
LVTX6_E+
/CONFIG
/STATUS
LVTX7_B-
VS_STATUS2V5
100
R11425
0 . 1 u F
16V
16V
C11407
0 . 1 u F
16V
16V
C11403
TD6-
TC2-
LVTX5_B+
1V2
VS_STATUS2V5
TCLK3-
100
R11444
FPGA_SCL
TCLK2+
FPGA_SDA
LVTX7_D-
TA1+
LVTX3_D+
LVTX1_CLK-
100
R11422
TDI_FPGA
2SC3052
Q11404
E
B
C
TC5-
1K
R11493
100
R11412
330
R11449
MSEL[0]
0 . 1 u F
16V
16V
C11405
/CE
TD3-
TE4-
LVTX1_E+
LVTX2_A-
MSEL[3]
22
R11497
TCLK4+
TE2+
LVTX8_E+
/RESET2V5
TD1+
/STATUS
LVTX6_D-
100
R11429
LVTX4_A-
LVTX2_D+
TB7+
0 . 1 u F
16V
16V
C11408
LVTX5_A+
22
R11490
LVTX5_C-
LVTX3_A+
TE6+
10K
R11479
1V2
MSEL[2]
MSEL[1]
2V5
LVTX5_CLK-
LVTX8_A-
0 . 1 u F
16V
C11418
0 . 1 u F
16V
16V
C11412
54.0000MHz
X11400
4
VDD
1
TRISTATE/OPEN
2
GND
3
OUTPUT
10K
R11448
TE8-
SDA2V5
TC5+
LVTX8_A+
4.7K
R11489
LVTX3_A-
SCL2V5
TE7+
LVTX7_A+
TB8+
TA8+
0
OPT
R11476
18pF
50V
50V
OPT
C11410
22
R11496
+3.3V
2V5
LVTX3_B+
LVTX8_D+
2V5
TMS_FPGA
TB3-
5.6K
R11469
100
R11440
18pF
50V
50V
OPT
C11413
100
R11433
TC8+
100
R11406
+3.3V
TA7-
0
R11467
2K
R11463
TD7+
100
R11432
LVTX1_D+
ASDO
3D_SYNC_OUT
100
R11415
TA3+
2K
R11464
1K
R11492
MSEL[3]
TCLK6+
TB6-
LVTX4_D+
LVTX4_E-
FDV301N
Q11401
G
D
S
/CE
MSEL[2]
EPCS16SI8N_
IC11401
3
VCC
2
DATA
4
GND
1
NCS
5
ASDI
6
DCLK
7
VCC_1
8
VCC_2
2V5
LVTX1_A+
0 . 1 u F
16V
16V
C11404
0 . 1 u F
16V
16V
C11401
TD5+
TB4-
LVTX2_C-
0 . 1 u F
16V
16V
C11415
FDV301N
Q11403
G
D
S
/CSO
2V5
100
R11442
LVTX8_C-
LVTX1_C+
TB3+
LVTX3_CLK-
TB5+
TB2+
TA4-
LVTX2_C+
TB5-
LVTX2_A+
TD7-
100
R11439
TC3+
TA5-
LVTX4_E+
TCLK6-
LVTX5_D+
100
R11430
TC6-
LVTX7_E+
TC3-
TE1+
LVTX7_D+
100
R11421
100
R11413
TD1-
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
CONFIG_DONE
LVTX4_D-
LVTX7_B+
DATA0
LVTX7_E-
LVTX4_A+
100
R11426
LVTX2_B-
LVTX6_CLK-
1K
R11455
OPT
100
R11408
22
R11465
LVTX4_B+
2SC3052
Q11402
E
B
C
TC6+
2SC3052
Q11405
E
B
C
1V2
SDA2V5
2V5
/RESET2V5
1V2
18pF
50V
50V
OPT
C11411
TE3-
2V5
LVTX4_CLK+
+3.3V
100
R11438
2V5
DCLK
10K
R11454
LVTX6_D+
LVTX1_A-
TD8-
TDO_FPGA
I2C_SCL
LVTX7_C-
10K
R11487
TD6+
LVTX4_B-
TE1-
LVTX3_C-
22
R11494
TB8-
TE7-
LVTX2_E+
22
R11457
TCLK8+
100
R11447
TE5-
LVTX3_E+
LVTX6_B-
TCK_FPGA
100
R11401
100
R11445
1K
R11450
TA7+
10K
R11452
TC2+
TB1+
22
R11456
TA2+
0
OPT
R11478
4.7K
R11459
2V5
LVTX5_C+
/CSO
TD8+
TA6-
SYSCLK
0
R11474
LVTX2_B+
100
R11403
TCK_FPGA
LVTX6_C-
100
R11405
5.6K
OPT
R11470
LVTX5_CLK+
2V5
10K
R11488
1V2
10K
R11453
0 . 1 u F
16V
16V
C11402
100
R11435
LVTX8_CLK+
TA3-
LVTX8_E-
22 OPT
R11466
/3D_FPGA_RESET
+3.3V
22
OPT
R11483
TE3+
LVTX6_A-
TD5-
100
R11416
TE5+
100
R11420
LVTX5_D-
100
R11446
2V5
+3.3V
TDI_FPGA
SCL2V5
LVTX8_CLK-
10K
R11482
0 . 1 u F
16V
16V
C11409
2V5
2SC3052
Q11406
E
B
C
MSEL[0]
LVTX5_E-
LVTX4_C+
I2C_SDA
TA6+
LVTX6_C+
LVTX3_CLK+
/3D_FPGA_RESET
TB7-
VS_STATUS2V5
LVTX6_A+
100
R11428
LVTX2_D-
TC8-
LVTX3_C+
LVTX4_CLK-
TD3+
TCLK1-
100
R11441
CONFIG_DONE
LVTX5_A-
TCLK5-
100
R11409
LVTX2_CLK+
LVTX1_B-
LVTX5_E+
LVTX2_CLK-
LVTX1_D-
0 . 1 u F
16V
16V
C11406
1V2
100
R11407
100pF
50V
50V
C11416
1V2
TE4+
LVTX8_D-
100
R11437
TCLK4-
TMS_FPGA
TC7-
100
R11418
100
R11436
100
R11410
KIA7029AF
IC11402
2
G
3
O
1
I
22
R11495
100
R11402
LVTX3_D-
TA4+
LVTX8_B+
TC7+
LVTX1_E-
JTP-1127WEM
SW11400
1
2
4
3
TB6+
TCLK1+
LVTX6_E-
TC1+
1K
R11491
MSEL[1]
TCLK8-
10K
R11484
ASDO
TE2-
TCLK7-
100
R11427
TA2-
LVTX2_E-
LVTX6_CLK+
100
R11431
LVTX1_B+
LVTX5_B-
1V2
TCLK3+
100
R11400
0
R11458
TC1-
LVTX7_CLK+
LVTX7_A-
100
R11417
LVTX7_C+
+3.3V
LVTX1_C-
2V5
TA1-
10uF
16V
16V
C11414
10K
R11480
TB4+
+3.3V
TD2-
4.7K
OPT
R11481
LVTX4_C-
100
R11411
TA5+
100
R11419
BLM18PG121SN1D
L11400
TD4-
5.6K
OPT
R11471
TCLK2-
10pF
C11417
0
R11462
OPT
TCLK7+
0
R11475
LVTX6_B+
LVTX7_CLK-
TC4+
100
R11423
TC4-
TE6-
LVTX8_B-
100
R11404
TB1-
100
R11434
TD2+
LVTX3_E-
LVTX3_B-
LVTX8_C+
TE8+
2V5
100
R11414
TD4+
TCLK5+
/FPGA_RESET
/CONFIG
DCLK
22
1/16W
AR11400
12507WR-10L
P11400
1
2
3
4
5
6
7
8
9
10
11
EP3C55F484C6N
IC11400
F6
VCCD_PLL3
F5
GNDA3
G6
VCCA3
G4
B 1 _ I O [ 0 ]
G3
B 1 _ I O [ 1 ]
B2
B 1 _ I O [ 2 ]
B1
B 1 _ I O [ 3 ]
G5
B 1 _ I O [ 4 ]
E4
B 1 _ I O [ 5 ]
E3
B 1 _ I O [ 6 ]
C2
B 1 _ I O [ 7 ]
C1
B 1 _ I O [ 8 ]
D2
B 1 _ I O [ 9 ]
D1
B 1 _ I O [ 1 0 ]
H7
B 1 _ I O [ 1 1 ]
H6
B 1 _ I O [ 1 2 ]
J 6
B 1 _ I O [ 1 3 ]
H4
B 1 _ I O [ 1 4 ]
H3
B 1 _ I O [ 1 5 ]
E2
B 1 _ I O [ 1 6 ]
E1
B 1 _ I O [ 1 7 ]
F2
B 1 _ I O [ 1 8 ]
F1
B 1 _ I O [ 1 9 ]
J 5
B 1 _ I O [ 2 0 ]
H5
B 1 _ I O [ 2 1 ]
K6
nSTATUS
J 7
B 1 _ I O [ 2 2 ]
K7
B 1 _ I O [ 2 3 ]
J 4
B 1 _ I O [ 2 4 ]
H2
B 1 _ I O [ 2 5 ]
H1
B 1 _ I O [ 2 6 ]
J 3
B 1 _ I O [ 2 7 ]
J 2
B 1 _ I O [ 2 8 ]
J 1
B 1 _ I O [ 2 9 ]
K2
DCLK
K1
B 1 _ I O [ 3 0 ]
K5
nCONFIG
L5
TDI
L2
TCK
L1
TMS
L4
TDO
L3
nCE
G2
CLK0
G1
CLK1
EP3C55F484C6N
IC11400
T2
CLK2
T1
CLK3
L6
B 2 _ I O [ 0 ]
M6
B 2 _ I O [ 1 ]
M2
B 2 _ I O [ 2 ]
M1
B 2 _ I O [ 3 ]
M4
B 2 _ I O [ 4 ]
M3
B 2 _ I O [ 5 ]
N2
B 2 _ I O [ 6 ]
N1
B 2 _ I O [ 7 ]
M5
B 2 _ I O [ 8 ]
P2
B 2 _ I O [ 9 ]
P1
B 2 _ I O [ 1 0 ]
R2
B 2 _ I O [ 1 1 ]
R1
B 2 _ I O [ 1 2 ]
N5
B 2 _ I O [ 1 3 ]
P4
B 2 _ I O [ 1 4 ]
P3
B 2 _ I O [ 1 5 ]
U2
B 2 _ I O [ 1 6 ]
U1
B 2 _ I O [ 1 7 ]
V2
B 2 _ I O [ 1 8 ]
V1
B 2 _ I O [ 1 9 ]
P5
B 2 _ I O [ 2 0 ]
N6
B 2 _ I O [ 2 1 ]
R4
B 2 _ I O [ 2 2 ]
R3
B 2 _ I O [ 2 3 ]
W2
B 2 _ I O [ 2 4 ]
W1
B 2 _ I O [ 2 5 ]
Y2
B 2 _ I O [ 2 6 ]
Y1
B 2 _ I O [ 2 7 ]
T3
B 2 _ I O [ 2 8 ]
N7
B 2 _ I O [ 2 9 ]
P7
B 2 _ I O [ 3 0 ]
AA2
B 2 _ I O [ 3 1 ]
AA1
B 2 _ I O [ 3 2 ]
V4
B 2 _ I O [ 3 3 ]
V3
B 2 _ I O [ 3 4 ]
P6
B 2 _ I O [ 3 5 ]
R5
B 2 _ I O [ 3 6 ]
T4
B 2 _ I O [ 3 7 ]
T5
B 2 _ I O [ 3 8 ]
R6
B 2 _ I O [ 3 9 ]
T6
VCCA1
U5
GNDA1
U6
VCCD_PLL1
EP3C55F484C6N
IC11400
VCCD_PLL4
V17
GNDA4
V18
VCCA4
U18
B 5 _ I O [ 0 ]
AA22
B 5 _ I O [ 1 ]
AA21
B 5 _ I O [ 2 ]
T17
B 5 _ I O [ 3 ]
T18
B 5 _ I O [ 4 ]
W20
B 5 _ I O [ 5 ]
W19
B 5 _ I O [ 6 ]
Y22
B 5 _ I O [ 7 ]
Y21
B 5 _ I O [ 8 ]
U20
B 5 _ I O [ 9 ]
U19
B 5 _ I O [ 1 0 ]
W22
B 5 _ I O [ 1 1 ]
W21
B 5 _ I O [ 1 2 ]
T20
B 5 _ I O [ 1 3 ]
T19
B 5 _ I O [ 1 4 ]
R17
B 5 _ I O [ 1 5 ]
P17
B 5 _ I O [ 1 6 ]
V22
B 5 _ I O [ 1 7 ]
V21
B 5 _ I O [ 1 8 ]
R20
B 5 _ I O [ 1 9 ]
U22
B 5 _ I O [ 2 0 ]
U21
B 5 _ I O [ 2 1 ]
R18
B 5 _ I O [ 2 2 ]
R19
B 5 _ I O [ 2 3 ]
N16
B 5 _ I O [ 2 4 ]
R22
B 5 _ I O [ 2 5 ]
R21
B 5 _ I O [ 2 6 ]
P20
B 5 _ I O [ 2 7 ]
P22
B 5 _ I O [ 2 8 ]
P21
B 5 _ I O [ 2 9 ]
N20
B 5 _ I O [ 3 0 ]
N19
B 5 _ I O [ 3 1 ]
N17
B 5 _ I O [ 3 2 ]
N18
B 5 _ I O [ 3 3 ]
N22
B 5 _ I O [ 3 4 ]
N21
B 5 _ I O [ 3 5 ]
M22
B 5 _ I O [ 3 6 ]
M21
B 5 _ I O [ 3 7 ]
M20
B 5 _ I O [ 3 8 ]
M19
B 5 _ I O [ 3 9 ]
M16
CLK7
T22
CLK6
T21
EP3C55F484C6N
IC11400
CLK5
G22
CLK4
G21
CONF_DONE
M18
MSEL0
M17
MSEL1
L18
MSEL2
L17
MSEL3
K20
B 6 _ I O [ 0 ]
L22
B 6 _ I O [ 1 ]
L21
B 6 _ I O [ 2 ]
K19
B 6 _ I O [ 3 ]
K22
B 6 _ I O [ 4 ]
K21
B 6 _ I O [ 5 ]
J 2 2
B 6 _ I O [ 6 ]
J 2 1
B 6 _ I O [ 7 ]
H22
B 6 _ I O [ 8 ]
H21
B 6 _ I O [ 9 ]
K17
B 6 _ I O [ 1 0 ]
K18
B 6 _ I O [ 1 1 ]
J 1 8
B 6 _ I O [ 1 2 ]
F22
B 6 _ I O [ 1 3 ]
F21
B 6 _ I O [ 1 4 ]
J 2 0
B 6 _ I O [ 1 5 ]
J 1 9
B 6 _ I O [ 1 6 ]
J 1 7
B 6 _ I O [ 1 7 ]
H20
B 6 _ I O [ 1 8 ]
H19
B 6 _ I O [ 1 9 ]
E22
B 6 _ I O [ 2 0 ]
E21
B 6 _ I O [ 2 1 ]
H18
B 6 _ I O [ 2 2 ]
H16
B 6 _ I O [ 2 3 ]
D22
B 6 _ I O [ 2 4 ]
D21
B 6 _ I O [ 2 5 ]
F20
B 6 _ I O [ 2 6 ]
F19
B 6 _ I O [ 2 7 ]
G18
B 6 _ I O [ 2 8 ]
H17
B 6 _ I O [ 2 9 ]
C22
B 6 _ I O [ 3 0 ]
C21
B 6 _ I O [ 3 1 ]
B22
B 6 _ I O [ 3 2 ]
B21
B 6 _ I O [ 3 3 ]
C20
B 6 _ I O [ 3 4 ]
D20
B 6 _ I O [ 3 5 ]
F17
B 6 _ I O [ 3 6 ]
G17
VCCA2
F18
GNDA2
E18
VCCD_PLL2
E17
EP3C55F484C6N
IC11400
B 7 _ I O [ 0 ]
F16
B 7 _ I O [ 1 ]
E16
B 7 _ I O [ 2 ]
F15
B 7 _ I O [ 3 ]
G16
B 7 _ I O [ 4 ]
G15
B 7 _ I O [ 5 ]
F14
B 7 _ I O [ 6 ]
C18
B 7 _ I O [ 7 ]
D18
B 7 _ I O [ 8 ]
D17
B 7 _ I O [ 9 ]
C19
B 7 _ I O [ 1 0 ]
D19
B 7 _ I O [ 1 1 ]
A20
B 7 _ I O [ 1 2 ]
B20
B 7 _ I O [ 1 3 ]
C17
B 7 _ I O [ 1 4 ]
B19
B 7 _ I O [ 1 5 ]
A19
B 7 _ I O [ 1 6 ]
A18
B 7 _ I O [ 1 7 ]
B18
B 7 _ I O [ 1 8 ]
D15
B 7 _ I O [ 1 9 ]
E15
B 7 _ I O [ 2 0 ]
G14
B 7 _ I O [ 2 1 ]
G13
B 7 _ I O [ 2 2 ]
A17
B 7 _ I O [ 2 3 ]
B17
B 7 _ I O [ 2 4 ]
A16
B 7 _ I O [ 2 5 ]
B16
B 7 _ I O [ 2 6 ]
C15
B 7 _ I O [ 2 7 ]
E14
B 7 _ I O [ 2 8 ]
F13
B 7 _ I O [ 2 9 ]
A15
B 7 _ I O [ 3 0 ]
B15
B 7 _ I O [ 3 1 ]
C13
B 7 _ I O [ 3 2 ]
D13
B 7 _ I O [ 3 3 ]
E13
B 7 _ I O [ 3 4 ]
A14
B 7 _ I O [ 3 5 ]
B14
B 7 _ I O [ 3 6 ]
A13
B 7 _ I O [ 3 7 ]
B13
B 7 _ I O [ 3 8 ]
E12
B 7 _ I O [ 3 9 ]
E11
B 7 _ I O [ 4 0 ]
F11
CLK8
A12
CLK9
B12
EP3C55F484C6N
IC11400
B 8 _ I O [ 0 ]
A11
B 8 _ I O [ 1 ]
B11
B 8 _ I O [ 2 ]
D10
B 8 _ I O [ 3 ]
E10
B 8 _ I O [ 4 ]
A10
B 8 _ I O [ 5 ]
B10
B 8 _ I O [ 6 ]
A9
B 8 _ I O [ 7 ]
B9
B 8 _ I O [ 8 ]
C10
B 8 _ I O [ 9 ]
G11
B 8 _ I O [ 1 0 ]
A8
B 8 _ I O [ 1 1 ]
B8
B 8 _ I O [ 1 2 ]
A7
B 8 _ I O [ 1 3 ]
B7
B 8 _ I O [ 1 4 ]
A6
B 8 _ I O [ 1 5 ]
B6
B 8 _ I O [ 1 6 ]
E9
B 8 _ I O [ 1 7 ]
C8
B 8 _ I O [ 1 8 ]
C7
B 8 _ I O [ 1 9 ]
D8
B 8 _ I O [ 2 0 ]
E8
B 8 _ I O [ 2 1 ]
A5
B 8 _ I O [ 2 2 ]
B5
B 8 _ I O [ 2 3 ]
G10
B 8 _ I O [ 2 4 ]
F10
B 8 _ I O [ 2 5 ]
C6
B 8 _ I O [ 2 6 ]
D7
B 8 _ I O [ 2 7 ]
A4
B 8 _ I O [ 2 8 ]
B4
B 8 _ I O [ 2 9 ]
F8
B 8 _ I O [ 3 0 ]
G8
B 8 _ I O [ 3 1 ]
A3
B 8 _ I O [ 3 2 ]
B3
B 8 _ I O [ 3 3 ]
D6
B 8 _ I O [ 3 4 ]
E7
B 8 _ I O [ 3 5 ]
C3
B 8 _ I O [ 3 6 ]
C4
B 8 _ I O [ 3 8 ]
F7
B 8 _ I O [ 3 9 ]
G7
B 8 _ I O [ 4 0 ]
F9
B 8 _ I O [ 4 1 ]
E6
B 8 _ I O [ 4 2 ]
E5
B 8 _ I O [ 4 3 ]
G9
3.3K
R11468
2K
R11461
2K
R11460
TDO_FLASH
TMS_FLASH
TDI_FLASH
TCK_FLASH
22
R11144
2SC3052
Q11141
E
B
C
4.7K
R11143
FPGA_D/L_CTRL
2V5
/CE
10K
R11142
0
R11141
/CONFIG
BLM18PG121SN1D
L11401
OPT
+3.3V
MDS62110208
GAS1
OPT
MDS62110208
GAS2
OPT
MDS62110208
GAS6
OPT
MDS62110208
GAS7
OPT
MDS62110208
GAS3
OPT
MDS62110208
GAS5
OPT
MDS62110208
GAS4
OPT
MDS62110208
GAS8
OPT
0
OPT
R21500
0
R21502
0
R21501
0
R21504
0
R21505
OPT
0
R11499
0
OPT
R11498
0
OPT
R21503
22
FPGA_DL
R21506
22
FPGA_DL
R21508
22
R11485
22
R11486
22
R11472
33
FPGA_DL
R21509
33
FPGA_DL
R21507
27
R11473
MDS62110208
OPT
GAS11
MDS62110208
OPT
GAS12
MDS62110208
OPT
GAS10
MDS62110208
OPT
GAS9
MDS62110208
OPT
GAS13
MDS62110208
OPT
GAS14
F P G A I 2 C L e v e l S h i f t ( 3 . 3 V < - > 2 . 5 V )
3D + 240 FRC + TCON BOARD
9
EP3C55_C6N (FPGA IC)
10
I R E m i t t e r V s y n c L e v e l S h i f t ( 2 . 5 V t o 3 . 3 V )
F P G A R e s e t L e v e l S h i f t e r ( 3 . 3 V t o 2 . 5 V )
2 0 0 9 . 1 1 . 1 3
FPGA DOWNLOAD CONTROL
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