47LD650H (CHASSIS:LD03Y) - LG TV Service Manual (repair manual). Page 41

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THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
10
R8911
FRC_DQU[2]
DDR3_DQU[1]
2200pF
C8928
H5TQ1G63BFR-12C
IC8901
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J 7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J 3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J 1
NC_2
J 9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J 2
VSS_6
J 8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
10
R8909
POWER_ON/OFF2_2
0.1uF
C8907
FRC_DQL[1]
FRC_DMU
10
AR8901
FRC_ODT
1K
1
%
R8903
FRC_DQL[7]
DDR3_DQSLB
NR8040T3R6N
3.6uH
L8906
1K
1
%
R8901
DDR3_DMU
FRC_DQU[7]
10uF
25V
C8935
FRC_BA0
DDR3_DQL[3]
FRC_DQSU
10uF
C8903
DDR3_A[9]
DDR3_DQL[2]
L8905
FRC_A[4]
3.3K
1%
R8928
FRC_DQL[0]
L8901
3.9K
1%
R8929
+1.5V_MEMC
CIC21J501NE
L8904
DDR3_A[0-12]
FRC_A[5]
22uF
10V
C8939
+3.3V_MEMC
DDR3_DQU[2]
10uF
10V
C8901
DDR3_DQU[5]
DDR3_DQU[3]
DDR3_A[2]
FRC_A[9]
FRC_A[6]
D1.5V_DDR3
AOZ1072AI
IC8902
3
AGND
2
VIN
4
FB
1
PGND
5
COMP
6
EN
7
LX_1
8
LX_2
DDR3_WEB
10uF
25V
C8926
+1.5V_MEMC
240
1%
R8915
+12V
10
R8913
10K
R8926
10
R8907
270
1%
R8923
0.1uF
C8919
DDR3_MCLK
DDR3_A[12]
0.1uF
C8916
DDR3_BA1
DDR3_DQU[0]
DDR3_CKE
0.1uF
C8910
FRC_DQL[4]
DDR3_DQL[6]
FRC_A[0]
DDR3_A[0]
D1.5V_DDR3
10uF
16V
C8932
D1.5V_DDR3
0.1uF
C8914
10
AR8906
0.1uF
C8906
0.1uF
C8922
DDR3_MCLKB
FRC_A[7]
DDR3_BA0
DDR3_DQSUB
DDR3_DMU
FRC_A[2]
FRC_MCLKB
1K
1
%
R8904
10
AR8908
FRC_DQSUB
DDR3_DQL[4]
10
AR8904
22uF
10V
C8930
0 . 1 u F
16V
C8902
DDR3_CKE
DDR3_DQU[7]
10
R8912
DDR3_DQSU
D1.5V_DDR3
10
R8905
FRC_RASB
FRC_A[1]
DDR3_DQSL
10
AR8905
DDR3_A[4]
NR8040T3R6N
3.6uH
L8903
FRC_DQL[5]
FRC_CASB
DDR3_A[3]
+3.3V_MEMC
DDR3_BA2
FRC_DQL[3]
FRC_A[8]
DDR3_ODT
DDR3_BA0
DDR3_A[7]
10
AR8903
+12V
FRC_DQSL
POWER_ON/OFF2_1
0.1uF
C8918
1K
1
%
R8902
FRC_DQU[3]
10K
1%
R8922
MVREFDQ
FRC_DML
DDR3_A[10]
DDR3_MCLKB
DDR3_MCLK
DDR3_WEB
CIC21J501NE
L8902
100pF
50V
OPT
C8929
12K
1%
R8930
DDR3_RASB
10K
R8917
FRC_A[10]
DDR3_DQSLB
0.1uF
C8917
DDR3_A[5]
FRC_BA2
FRC_DQU[5]
10
R8914
FRC_WEB
DDR3_CASB
9.1K
R8919
DDR3_CASB
DDR3_DQL[7]
10
R8906
DDR3_DQL[5]
DDR3_A[6]
D1.5V_DDR3
DDR3_DQL[0-7]
10uF
C8933
4.7K
1%
R8921
MVREFCA
0.1uF
C8920
DDR3_A[11]
DDR3_DML
DDR3_DML
DDR3_RESETB
0 . 1 u F
16V
C8931
0.1uF
C8924
FRC_DQL[2]
0.1uF
C8915
150
OPT
R8916
DDR3_DQU[0-7]
FRC_A[12]
0 . 1 u F
16V
C8940
DDR3_ODT
10
R8910
DDR3_BA2
FRC_DQU[6]
FRC_DQU[1]
0.1uF
C8911
DDR3_DQSU
FRC_MCLK
27K
1%
R8920
FRC_BA1
1
R8925
10
R8908
FRC_DQU[4]
DDR3_RESETB
DDR3_A[1]
0.1uF
C8912
10uF
25V
C8936
3300pF
C8937
FRC_DQU[0]
10
AR8909
0.1uF
C8909
1000pF
OPT
C8925
10uF
25V
C8927
DDR3_BA1
0.1uF
C8905
DDR3_A[8]
MVREFCA
FRC_A[11]
10K
R8918
0.1uF
C8913
DDR3_DQSUB
0.1uF
C8904
56
1%
R8924
DDR3_DQU[6]
100pF
50V
OPT
C8938
FRC_DQL[6]
10
AR8907
FRC_CKE
FRC_DDR3_RESETB
0.1uF
C8908
FRC_A[3]
D1.5V_DDR3
AOZ1072AI
IC8904
3
AGND
2
VIN
4
FB
1
PGND
5
COMP
6
EN
7
LX_1
8
LX_2
1000pF
OPT
C8923
DDR3_DQL[0]
FRC_DQSLB
0 . 1 u F
16V
C8934
MVREFDQ
+1.26V_MEMC
6.2K
R8927
DDR3_DQSL
10
AR8902
0.1uF
C8921
DDR3_DQU[4]
DDR3_RASB
AP1117EG-13 
IC8903
ADJ/GND
OUT
IN
DDR3_DQL[1]
K4B1G1646E-HCH9000
IC8901-*1
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J 7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J 3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J 1
NC_2
J 9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J 2
VSS_6
J 8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
DDR3_A[11]
DDR3_DQU[0]
DDR3_DQL[1]
DDR3_DQL[4]
DDR3_DQU[3]
DDR3_DQL[6]
DDR3_A[3]
DDR3_DQL[7]
DDR3_DQL[3]
DDR3_DQU[7]
DDR3_A[2]
DDR3_A[7]
DDR3_DQU[1]
DDR3_DQU[4]
DDR3_A[5]
DDR3_DQL[5]
DDR3_DQU[5]
DDR3_A[8]
DDR3_A[10]
DDR3_DQL[2]
DDR3_DQL[0]
DDR3_A[12]
DDR3_A[9]
DDR3_A[4]
DDR3_A[6]
DDR3_A[0]
DDR3_DQU[2]
DDR3_DQU[6]
DDR3_A[1]
R1
1074 mA
R2
URSA3 DDR3 1.5V
+3.3V_MEMC
R2
R1
V o u t = 0 . 8 * ( 1 + R 1 / R 2 )
2A
V o u t = 0 . 8 * ( 1 + R 1 / R 2 )
Close to DDR Power Pin
DDR3 1.5V By CAP - Place these Caps near Memory
2A
URSA3 CORE 1.26V
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