Read LG 47LD650H (CHASSIS:LD03Y) Service Manual online
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+3.3V_MEMC
RXA2-
RXC3-
RXC2-
10K
R9003
SCL1_3.3V
0.1uF
C9001
SCAN_BLK1/OPC_OUT
FRC_SPI_DI
CIC21J501NE
L9003
FRC_DQU[0-7]
1M
R9019
LVDS_TX_0_CLK_N
0
FRC_L/DIM
R9036
FRC_PWM0
10uF
C9008
LVDS_TX_0_DATA2_P
RXD4+
RXA4-
22
R9050
0 . 1 u F
C9033
+3.3V_MEMC
AVDD_DDR
FRC_DML
0 . 1 u F
C9036
100
R9014
12MHz
X9001
100
LD_SCAN
R9045
820
R9033
100
R9035
0 . 1 u F
C9021
RXA1+
RXC0-
FRC_RASB
4.7K
URSA3_MIRROR
R9023
10
R9005
1K
OPT
R9042
LVDS_TX_1_DATA4_P
CIC21J501NE
L9005
RXD3-
FRC_PWM0
10uF
C9032
100
R9054
0 . 1 u F
C9029
10
R9001
1K
R9039
FRC_DDR3_RESETB
10uF
C9016
RXDCK+
+3.3V_MEMC
0 . 1 u F
C9012
+3.3V_MEMC
LVDS_TX_1_DATA2_N
RXB2+
22
OPT
R9052
RXBCK-
4.7K
URSA3_LOCAL_DIMMING
R9032
RXC1-
RXA0-
0 . 1 u F
C9030
22pF
C9037
LVDS_TX_1_DATA1_N
URSA3_SDA
AVDD_MEMPLL
RXC1+
FRC_CONF1
VDDC
0 . 1 u F
C9020
0 . 1 u F
C9019
+3.3V_MEMC
RXACK+
10uF
C9005
LVDS_TX_1_DATA2_P
0 . 1 u F
C9026
AVDD
0 . 1 u F
C9034
10uF
C9010
100
R9015
1K
OPT
R9040
RXB1+
FRC_CASB
RXA1-
4.7K
URSA3_NON_GIP
R9027
FRC_RESET
CIC21J501NE
L9001
GVDD_ODD
RXC4+
RXB3+
URSA3_SDA
0 . 1 u F
C9015
RXB0-
100
R9056
CIC21J501NE
L9008
RXD2-
LVDS_TX_1_DATA0_P
AVDD_PLL
FRC_PWM1
VDDC
RXD2+
1K
OPT
R9037
10uF
C9002
RXA3+
100
R9020
0
MINI_LVDS
R9034
LVDS_TX_0_DATA0_P
FRC_PWM1
RXC0+
GCLK4
100
R9006
+3.3V_MEMC
FRC_SPI_CK
RXB4-
100
R9055
4.7K
URSA3_NON_MIRROR
R9024
22
R9049
FRC_DQSL
FRC_SPI_CK
FRC_DQSU
RXDCK-
RXB1-
10uF
C9011
0 . 1 u F
C9040
+3.3V_MEMC
4.7K
URSA3_NON_LOCAL_DIMMING
R9031
FRC_BA1
AVDD_LVDS
LVDS_TX_0_DATA1_N
100
R9058
LVDS_TX_1_DATA3_P
LGE7378A[FRC_TCON_URSA3]
URSA3
IC9001
DDR3_A0/DDR2_NC
E2
DDR3_A1/DDR2_A6
U6
DDR3_A2/DDR2_A7
E3
DDR3_A3/DDR2_A1
G2
DDR3_A4/DDR2_CASZ
R4
DDR3_A5/DDR2_A10
G1
DDR3_A6/DDR2_A0
U5
DDR3_A7/DDR2_A5
F3
DDR3_A8/DDR2_A2
T5
DDR3_A9/DDR2_A9
F1
DDR3_A10/DDR2_A11
R6
DDR3_A11/DDR2_A4
R5
DDR3_A12/DDR2_A8
T6
DDR3_BA0/DDR2_BA2
G3
DDR3_BA1/DDR2_ODT
U4
DDR3_BA2/DDR2_A12
E1
DDR3_MCLK/DDR2_MCLK
U1
DDR3_MCLKZ/DDR2_MCLKZ
U2
DDR3_CKE/DDR2_RASZ
T4
DDR3_ODT/DDR2_BA1
H2
DDR3_RASZ/DDR2_WEZ
J 1
DDR3_CASZ/DDR2_CKE
H3
DDR3_WEZ/DDR2_BA0
H1
DDR3_RESET/DDR2_A3
F2
DDR2_DQS0/DDR3_DQS0
M3
DDR2_DQS1/DDR3_DQS1
N2
DDR2_DQSB0/DDR3_DQSB0
N1
DDR2_DQSB1/DDR3_DQSB1
N3
DDR2_DQ7/DDR3_DQM0
R2
DDR2_DQ11/DDR3_DQM1
K3
DDR2_DQ6/DDR3_DQ0
K2
DDR2_DQ0/DDR3_DQ1
R3
DDR2_DQ1/DDR3_DQ2
K1
DDR2_DQ2/DDR3_DQ3
T1
DDR2_DQ4/DDR3_DQ4
J 2
DDR2_NC/DDR3_DQ5
T3
DDR2_DQ3/DDR3_DQ6
J 3
DDR2_DQ5/DDR3_DQ7
T2
DDR2_DQ8/DDR3_DQ8
P2
DDR2_DQ14/DDR3_DQ9
L3
DDR2_DQ13/DDR3_DQ10
R1
DDR2_DQ12/DDR3_DQ11
L1
DDR2_DQ15/DDR3_DQ12
P1
DDR2_DQ9/DDR3_DQ13
L2
DDR2_DQ10/DDR3_DQ14
P3
DDR2_DQM1/DDR3_DQ15
M1
DDR2_DQM0/DDR3_NC
M2
I2CM_SDA
C9
I2CM_SCL
D9
I2CM_SDA2_L
P7
I2CM_SCL2_L
N8
I2CM_SDA2_R
P9
I2CM_SCL2_R
N10
AVDD_1
F8
AVDD_2
F9
AVDD_DDR_1
L5
AVDD_DDR_2
L6
AVDD_DDR_3
L7
AVDD_DDR_4
L8
AVDD_DDR_5
M7
AVDD_DDR_6
M8
AVDD_LVDS_1
G12
AVDD_LVDS_2
H12
AVDD_LVDS_3
J12
AVDD_LVDS_4
K12
AVDD_MEMPLL
M6
AVDD_PLL_1
F11
AVDD_PLL_2
F12
DVDD_DDR[1.26V]
J5
VDD_EVEN
E16
VDD_ODD
E17
VDDC_1
F6
VDDC_2
F7
VDDC_3
G5
VDDC_4
G6
VDDC_5
G7
VDDC_6
H5
VDDC_7
H6
VDDC_8
J6
VDDP_1
G11
VDDP_2
K5
VDDP_3
K6
VDDP_4
M10
VDDP_5
M11
VSS_1
C10
VSS_2
C12
VSS_3
G8
VSS_4
G9
VSS_5
G10
VSS_6
H7
VSS_7
H8
VSS_8
H9
VSS_9
H10
VSS_10
H11
VSS_11
J4
VSS_12
J7
VSS_13
J8
VSS_14
J9
VSS_15
J10
VSS_16
J11
VSS_17
K7
VSS_18
K8
VSS_19
K9
VSS_20
K10
VSS_21
K11
VSS_22
L9
VSS_23
L10
VSS_24
L11
VSS_25
M9
VSS_26
N4
VSS_27
P6
A10
A10
A11
A11
A12
A12
B10
B10
B11
B11
B12
B12
C11
C11
D11
D11
TESTPIN
L13
VB1_TEST
F10
A0P/RV0+
B14
A0M/RV0-
A14
A1P/RV1+
C14
A1M/RLV1-
C15
A2P/RV2+
A15
A2M/RV2-
B15
ACKP/R3+
B16
ACKM/RV3-
A16
A3P/RV4+
A17
A3M/RV4-
B17
A4P/RV5+
C16
A4M/RV5-
C17
B0P/RV6+
D16
B0M/RV6-
D17
B1P/RV7+
D15
B1M/RV7-
E15
B2P/RV8+
F16
B2M/RV8-
F17
BCKP/WPWM
F15
BCKM/OPT_P
G15
B3P/OPT_N
G17
B3M/FLK
G16
B4P/GCLK6
H16
B4M/GLCK5
H17
C0P/LV0+
H15
C0M/LV0-
J 1 5
C1P/LV1+
J 1 7
C1M/LV1-
J 1 6
C2P/LV2+
K16
C2M/LV2-
K17
CCKP/LV3+
K15
CCKM/LV3-
L15
C3P/LV4+
L17
C3M/LV4-
L16
C4P/LV5+
M16
C4M/LV5-
M17
D0P/LV6+
M15
D0M/LV6-
N15
D1P/LV7+
N17
D1M/LV7-
N16
D2P/LV8+
P15
D2M/LV8-
R15
DCKP/GOE
R17
DCKM/GSC/GCLK3
R16
D3P/GSP_R
T16
D3M/GSP
T17
D4P/SOE
T15
D4M/POL
U17
GCLK4
P16
GCLK2
P17
I2CS_SDA
D1
I2CS_SCL
D2
PWM0
P14
PWM1
R14
LPLL_FBCLK
B13
LPLL_OUTCLK
U16
LPLL_REFIN
A13
RECKP
A2
RECKN
B2
RE0P
A4
RE0N
B4
RE1P
C3
RE1N
C4
RE2P
B3
RE2N
A3
RE3P
C1
RE3N
C2
RE4P
B1
RE4N
A1
ROCKP
A6
ROCKN
B6
RO0P
A8
RO0N
B8
RO1P
C7
RO1N
C8
RO2P
B7
RO2N
A7
RO3P
C5
RO3N
C6
RO4P
B5
RO4N
A5
XTALO
A9
XTALI
B9
GPIO[0]
K14
GPIO[1]
J13
GPIO[2]
H14
GPIO[3]
G13
GPIO[4]
F14
GPIO[5]
E13
GPIO[8]
D3
GPIO[9]
D4
GPIO[10]
E4
GPIO[12]
D5
GPIO[13]
D7
GPIO[14]
F4
M_S_PIF_CLK_1
R7
M_S_PIF_CLK_2
U8
M_S_PIF_CS
U7
M_S_PIF_DA1
T8
M_S_PIF_FC
T7
S_M_PIF_CLK
U14
S_M_PIF_CS
U15
S_M_PIF_DA0
R13
S_M_PIF_DA1
T13
S_M_PIF_FC
T14
LTD_CLK_L
T10
LTD_CLK_R
T11
LTD_DA0_L
R10
LTD_DA0_R
U11
LTD_DA1_L
R9
LTD_DA1_R
U12
LTD_DE_L
U10
LTD_DE_R
R11
OP_SYNC_L
U9
OP_SYNC_R
R12
PLL_LOCK_L
T9
PLL_LOCK_R
T12
SOFT_RST_L
R8
SOFT_RST_R
U13
SPI_CK
P13
SPI_CZ
N14
SPI_DI
N12
SPI_DO
N13
RESET
M14
REXT
C13
LVDS_TX_0_DATA4_P
10
R9002
MX25L4005CM2I-12G
EAN61009401
URSA3_FLASH_MACRONIX
IC9000
3
WP#
2
SO
4
GND
1
CS#
5
S I
6
SCLK
7
HOLD#
8
VCC
RXB3-
FRC_SPI_DI
W25X40BVSSIG
URSA3_FLASH_WINBOND_NEW
IC9000-*1
3
WP
2
DO[IO1]
4
GND
1
CS
5
D I [ I O 0 ]
6
CLK
7
HOLD
8
VCC
RXD4-
10
R9004
+3.3V_MEMC
LVDS_TX_0_DATA3_P
GCLK2
RXA2+
URSA3_SDA
1K
R9038
LVDS_TX_0_DATA3_N
1K
OPT
R9044
RXC2+
AVDD_MEMPLL
10uF
C9004
22
R9048
FRC_BA2
W25X40VSSIG
EAN35097301
URSA3_FLASH_WINBOND_OLD
IC9000-*2
3
WP
2
DO
4
GND
1
CS
5
DIO
6
CLK
7
HOLD
8
VCC
0
R9059
4.7K
URSA3_LVDS
R9026
4.7K
URSA3_SCANNING_OFF
R9030
AVDD_PLL
RXD3+
GVDD_EVEN
FRC_WEB
0 . 1 u F
C9027
RXD1-
FRC_CKE
RXBCK+
100
R9008
RXACK-
FRC_DMU
AVDD
LVDS_TX_1_CLK_N
FRC_DQSLB
LVDS_TX_1_DATA4_N
CIC21J501NE
L9006
URSA3_SCL
VDDP
RXB0+
100
LD_SCAN
R9046
100
R9009
FRC_PWM1
VDDC
SDA1_3.3V
RXB4+
100
R9053
SDA3_3.3V
DPM_A
100
R9021
FRC_ODT
0 . 1 u F
C9009
0 . 1 u F
C9014
FRC_CONF0
+1.5V_MEMC
10uF
C9024
0
URSA3
R9018
FRC_PWM0
LVDS_TX_1_DATA3_N
FRC_SPI_CZ
RXD1+
LVDS_TX_1_DATA1_P
0 . 1 u F
C9018
H_CONV
FRC_CONF1
100
R9013
0 . 1 u F
C9003
0 . 1 u F
C9007
FRC_SPI_DO
RXCCK+
JTP-1127WEM
SW9001
1
2
4
3
100
R9017
CIC21J501NE
L9004
12505WS-04A00
P9001
1
2
3
4
5
AVDD_DDR
100
R9016
FRC_SPI_CZ
RXC4-
VDDP
V_SYNC
FRC_BA0
RXB2-
LVDS_TX_0_DATA2_N
10uF
C9023
FRC_DQL[0-7]
RXA3-
FRC_SPI_DO
0 . 1 u F
C9022
URSA3_SCL
1K
R9041
LVDS_TX_0_DATA1_P
RXD0+
100
R9057
4.7K
URSA3_SCANNING_ON
R9029
AVDD_LVDS
1K
R9043
FRC_CONF0
FRC_A[0-12]
10uF
C9017
22
OPT
R9051
LVDS_TX_1_CLK_P
10uF
C9039
100
R9010
0 . 1 u F
C9013
RXCCK-
LVDS_TX_1_DATA0_N
+1.26V_MEMC
100
R9012
+3.3V_MEMC
22pF
C9038
22
R9047
0 . 1 u F
C9035
CIC21J501NE
L9002
100
R9011
10uF
C9031
FRC_CONF0
RXA4+
0 . 1 u F
C9006
RXD0-
LVDS_TX_0_DATA4_N
4.7K
URSA3_GIP
R9028
LVDS_TX_0_DATA0_N
FRC_MCLKB
0 . 1 u F
C9025
4.7K
URSA3_MINI_LVDS
R9025
URSA3_SCL
FRC_DQSUB
LVDS_TX_0_CLK_P
0 . 1 u F
C9028
FRC_MCLK
SCAN_BLK2
CIC21J501NE
L9007
RXA0+
100
R9007
RXC3+
SCL3_3.3V
FRC_A[9]
FRC_A[5]
FRC_A[4]
FRC_A[2]
FRC_DQU[2]
FRC_A[10]
FRC_A[1]
FRC_A[6]
FRC_DQL[4]
FRC_DQU[0]
FRC_DQU[6]
FRC_DQU[1]
FRC_A[11]
FRC_A[7]
FRC_DQU[4]
FRC_A[12]
FRC_DQL[0]
FRC_DQL[3]
FRC_DQU[7]
FRC_DQL[7]
FRC_A[8]
FRC_DQL[5]
FRC_DQL[1]
FRC_A[0]
FRC_A[3]
FRC_DQU[3]
FRC_DQL[2]
FRC_DQU[5]
FRC_DQL[6]
S e r i a l F l a s h
HIGH
K14
NON_MIRROR
NON_GIP
LD
LVDS
SCAN_ON
I2C ADR: GPIO1: HI:B8 LOW:B4
CHIP_CONF: {GPIO8, PWM1, PWM0}
C H I P _ C O N F = 3
¡
1 ¡ f o n t / e n g / _ s y s f o n t . v e
C H I P _ C O N F = 3
¡ z e ’ 6 0 P r
f o n t 1 2
R9
LOW
U10
GIP
MINI_LVDS
R10
NON_LD
Separate DVDD_DDR Power
MIRROR
SCAN_OFF
T10
FRC OPTION
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