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Report No.: EM201200331-1 Application No.:ZJ00016958 Page 12 of 56
4.4 DWELL TIME
4.4.1 LIMITS
EN300 328 clause 4.3.4
The maximum dwell time shall be 0,4 s.
4.4.2TEST PROCEDURE
Remove the antenna from the EUT and then connect a low attenuation cable from the antenna port to the spectrum.
Set spectrum analyzer span = 0. centered on a hopping channel;
Set RBW = 1MHz and VBW ≥ 1MHz. Sweep = as necessary to capture the entire dwell time per hopping channel. Detector
Function = Peak. Trace = Max hold;
Use the marker-delta function to determine the dwell time. If this value varies with different modes of operation (e.g.. data rate.
modulation format. etc.). repeat this test for each variation. The limit is specified in one of the subparagraphs of this Section.
Submit this plot(s). An oscilloscope may be used instead of a spectrum analyzer.
Pre-test the 3 modulation to find GFSK and 8DPSK is worse case, so only record GFSK and 8DPSK test data.
Set spectrum analyzer span = 0. centered on a hopping channel;
Set RBW = 1MHz and VBW ≥ 1MHz. Sweep = as necessary to capture the entire dwell time per hopping channel. Detector
Function = Peak. Trace = Max hold;
Use the marker-delta function to determine the dwell time. If this value varies with different modes of operation (e.g.. data rate.
modulation format. etc.). repeat this test for each variation. The limit is specified in one of the subparagraphs of this Section.
Submit this plot(s). An oscilloscope may be used instead of a spectrum analyzer.
Pre-test the 3 modulation to find GFSK and 8DPSK is worse case, so only record GFSK and 8DPSK test data.
4.4.3 TEST RESULTS
The test period: T= 0.4 Second/Channel x 79 Channel = 31.6 s
1. Channel 0: 2.402GHz
DH1 time slot = 0.387 (ms) * (1600/(2*79)) * 31.6 = 123.840 ms
DH3 time slot = 1.632(ms) * (1600/(4*79)) * 31.6 = 261.120 ms
DH3 time slot = 1.632(ms) * (1600/(4*79)) * 31.6 = 261.120 ms
DH5 time slot = 2.896 (ms) * (1600/(6*79)) * 31.6 = 308.906 ms
2DH1 time slot = 0.396(ms) * (1600/(2*79)) * 31.6 = 126.720 ms
2DH3 time slot = 1.648(ms) * (1600/(4*79)) * 31.6 = 263.680 ms
2DH5 time slot = 1.680 (ms) * (1600/(6*79)) * 31.6 = 179.200 ms
3DH1 time slot = 0.405 (ms) * (1600/(2*79)) * 31.6 = 129.601 ms
3DH3 time slot = 1.648(ms) * (1600/(4*79)) * 31.6 = 263.680 ms
3DH5 time slot= 2.896 (ms) * (1600/(6*79)) * 31.6 = 308.906 ms
2DH1 time slot = 0.396(ms) * (1600/(2*79)) * 31.6 = 126.720 ms
2DH3 time slot = 1.648(ms) * (1600/(4*79)) * 31.6 = 263.680 ms
2DH5 time slot = 1.680 (ms) * (1600/(6*79)) * 31.6 = 179.200 ms
3DH1 time slot = 0.405 (ms) * (1600/(2*79)) * 31.6 = 129.601 ms
3DH3 time slot = 1.648(ms) * (1600/(4*79)) * 31.6 = 263.680 ms
3DH5 time slot= 2.896 (ms) * (1600/(6*79)) * 31.6 = 308.906 ms
2. Channel 39: 2.441GHz
DH1 time slot = 0.378 (ms) * (1600/(2*79)) * 31.6 = 126.720 ms
DH3 time slot = 1.632(ms) * (1600/(4*79)) * 31.6 = 261.120 ms
DH5 time slot = 2.896 (ms) * (1600/(6*79)) * 31.6 = 308.906 ms
2DH1 time slot = 0.396(ms) * (1600/(2*79)) * 31.6 = 128.960 ms
2DH3 time slot = 1.616(ms) * (1600/(4*79)) * 31.6 = 258.560 ms
2DH5 time slot = 1.680(ms) * (1600/(6*79)) * 31.6 = 179.200 ms
3DH1 time slot = 0.405(ms) * (1600/(2*79)) * 31.6 = 129.600 ms
3DH3 time slot =1.648(ms) * (1600/(4*79)) * 31.6 = 263.680 ms
3DH5 time slot =2.912(ms) * (1600/(6*79)) * 31.6 = 310.613 ms
DH3 time slot = 1.632(ms) * (1600/(4*79)) * 31.6 = 261.120 ms
DH5 time slot = 2.896 (ms) * (1600/(6*79)) * 31.6 = 308.906 ms
2DH1 time slot = 0.396(ms) * (1600/(2*79)) * 31.6 = 128.960 ms
2DH3 time slot = 1.616(ms) * (1600/(4*79)) * 31.6 = 258.560 ms
2DH5 time slot = 1.680(ms) * (1600/(6*79)) * 31.6 = 179.200 ms
3DH1 time slot = 0.405(ms) * (1600/(2*79)) * 31.6 = 129.600 ms
3DH3 time slot =1.648(ms) * (1600/(4*79)) * 31.6 = 263.680 ms
3DH5 time slot =2.912(ms) * (1600/(6*79)) * 31.6 = 310.613 ms
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