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D DR1_A13
D DR1_A11
D DR1_A10
D DR1_A9
D DR1_A8
D DR1_A7
D DR1_A6
D DR1_A5
D DR1_A4
D DR1_A3
D DR1_A2
D DR1_A1
D DR1_A0
D DR1_A12
D DR1_A13
D DR1_A11
D DR1_A10
D DR1_A9
D DR1_A8
D DR1_A7
D DR1_A6
D DR1_A5
D DR1_A4
D DR1_A3
D DR1_A2
D DR1_A1
D DR1_A0
D DR1_A12
DDR1_CLK1
DDR1_DQM2
DDR1_DQM3
DDR1_DQS2N
DDR1_DQS2P
DDR1_DQS3N
DDR1_DQS3P
DDR1_ODT23
DDR1_WEN
DDR1_CASN
DDR1_RASN
DDR1_CS1N
D DR1_CKE
DDR1_CLK1N
DDR1_CLK1
DD R1_BA0
DD R1_BA1
DD R1_BA2
DD R1_BA2
DD R1_BA1
DD R1_BA0
DDR1_CLK0
DDR1_CLK0N
D DR1_CKE
DDR1_CS0N
DDR1_RASN
DDR1_CASN
DDR1_WEN
DDR1_ODT01
DDR1_DQS1P
DDR1_DQS1N
DDR1_DQS0P
DDR1_DQS0N
DDR1_DQM1
DDR1_DQM0
+VREF_DDR
DDR1_D14
DDR1_D10
DDR1_D13
DDR1_D9
DDR1_D12
DDR1_D11
DDR1_D15
DDR1_D8
DDR1_D6
DDR1_D5
DDR1_D1
DDR1_D0
DDR1_D7
DDR1_D4
DDR1_D2
DDR1_D3
DDR1_D26
DDR1_D28
DDR1_D29
DDR1_D30
DDR1_D24
DDR1_D31
DDR1_D27
DDR1_D25
DDR1_D22
DDR1_D17
DDR1_D20
DDR1_D18
DDR1_D19
DDR1_D16
DDR1_D21
DDR1_D[23:16]
DDR1_D23
DDR1_CLK1N
DDR1_D[7:0]
D DR1_A[13:0]
DDR1_CLK0N
DDR1_CLK0
+VREF_DDR
DDR1_D[15:8]
GND
GND
GND
GND
+1V8
+1V8
DDR1_DQS1P
DDR1_DQS1N
DDR1_DQM1
DDR1_DQM0
DDR1_DQM2
DDR1_DQS0N
DDR1_DQM3
DDR1_DQS0P
DDR1_DQS3N
DDR1_DQS3P
DDR1_DQS2P
DDR1_DQS2N
DDR1_ODT23
DDR1_ODT01
DDR1_CKE
DDR1_BA1
DDR1_BA2
DDR1_BA0
DDR1_CLK1
DDR1_CLK1N
DDR1_CASN
DDR1_WEN
DDR1_RASN
DDR1_CS0N
DDR1_CS1N
DDR1_CLK0
DDR1_CLK0N
+VREF_DDR
DDR1_D[15:8]
DDR1_D[7:0]
DDR1_A[13:0]
DDR1_D[31:24]
DDR1_D[23:16]
DDR1_A[13:0]
_
_
(CLUSTER)
(CLUSTER)
5- DDR2 clock and DQS P/N traces must be routed as 100 Ohms Differential pairs. Traces width and gap according to PCB stackup.
4- Length of all Data signals between Byte Lane should be matched together (<400 mils).
BCM7440 DDR2 2x16 --> Design notes and Layout Guidelines:
1- Place 121 ohms clock termination at the end of the differencial trace.
2- Pin swaping can only be done on data lines inside each group of 8 bit (Byte Lane).
3- Length of all Data signals into a Byte Lane should be matched together (<100 mils).
1- Place 121 ohms clock termination at the end of the differencial trace.
2- Pin swaping can only be done on data lines inside each group of 8 bit (Byte Lane).
3- Length of all Data signals into a Byte Lane should be matched together (<100 mils).
6- When developing the PCB floor plan, the proximity of the DDR2 device to the memory controller is an important factor.
- To avoid the use of external address termination on high-speed DDR2, the address trace length should be less than 2.5in.
* If those requirements can not be reached, refer to JEDEC JESD79-2B standard for design rules and terminations.
* If those requirements can not be reached, refer to JEDEC JESD79-2B standard for design rules and terminations.
DDR2 BANK-1
DDR2-1L
DDR2-1H
121
R571
2
1
DDR2
64Mx16
FBGA 84
HYB18TC1G160CF-2.5
U18
BGA84
NC2
E2
NC1
A2
WE*
K3
VDD5
J9
VDD4
R1
VDD3
M9
VDD2
E1
VDD1
A1
VDDQ10
G9
VDDQ9
G7
VDDQ8
G1
VDDQ7
E9
VDDQ6
G3
VDDQ5
C9
VDDQ4
C7
VDDQ3
C3
VDDQ2
C1
VDDQ1
A9
VDDL
J1
A12
R2
A11
P7
RFU/A13
R8
A10/AP
M2
A9
P3
A8
P8
A7
P2
A6
N7
A5
N3
A4
N8
A3
N2
A2
M7
A1
M3
A0
M8
BA2
L1
BA1
L3
BA0
L2
CK
J8
CK*
K8
VREF
J2
CKE
K2
CS*
L8
RAS*
K7
CAS*
L7
ODT
K9
DQ15
B9
DQ14
B1
DQ13
D9
DQ12
D1
DQ11
D3
DQ10
D7
DQ9
C2
DQ8
C8
DQ7
F9
DQ6
F1
DQ5
H9
DQ4
H1
DQ3
H3
DQ2
H7
DQ1
G2
DQ0
G8
UDM
B3
LDM
F3
UDQS
B7
UDQS*/NU
A8
LDQS
F7
LDQS*/NU
E8
VSS5
P9
VSS4
N1
VSS3
J3
VSS2
E3
VSS1
A3
VSSQ10
H8
VSSQ9
H2
VSSQ8
F8
VSSQ7
F2
VSSQ6
E7
VSSQ5
D8
VSSQ4
D2
VSSQ3
B8
VSSQ2
B2
VSSQ1
A7
VSSDL
J7
RFU/A14
R3
RFU/A15
R7
DDR2
64Mx16
FBGA 84
HYB18TC1G160CF-2.5
U17
BGA84
NC2
E2
NC1
A2
WE*
K3
VDD5
J9
VDD4
R1
VDD3
M9
VDD2
E1
VDD1
A1
VDDQ10
G9
VDDQ9
G7
VDDQ8
G1
VDDQ7
E9
VDDQ6
G3
VDDQ5
C9
VDDQ4
C7
VDDQ3
C3
VDDQ2
C1
VDDQ1
A9
VDDL
J1
A12
R2
A11
P7
RFU/A13
R8
A10/AP
M2
A9
P3
A8
P8
A7
P2
A6
N7
A5
N3
A4
N8
A3
N2
A2
M7
A1
M3
A0
M8
BA2
L1
BA1
L3
BA0
L2
CK
J8
CK*
K8
VREF
J2
CKE
K2
CS*
L8
RAS*
K7
CAS*
L7
ODT
K9
DQ15
B9
DQ14
B1
DQ13
D9
DQ12
D1
DQ11
D3
DQ10
D7
DQ9
C2
DQ8
C8
DQ7
F9
DQ6
F1
DQ5
H9
DQ4
H1
DQ3
H3
DQ2
H7
DQ1
G2
DQ0
G8
UDM
B3
LDM
F3
UDQS
B7
UDQS*/NU
A8
LDQS
F7
LDQS*/NU
E8
VSS5
P9
VSS4
N1
VSS3
J3
VSS2
E3
VSS1
A3
VSSQ10
H8
VSSQ9
H2
VSSQ8
F8
VSSQ7
F2
VSSQ6
E7
VSSQ5
D8
VSSQ4
D2
VSSQ3
B8
VSSQ2
B2
VSSQ1
A7
VSSDL
J7
RFU/A14
R3
RFU/A15
R7
121
R572
2
1
0.1UF
C659
1
2
0.1UF
C656
1
2
0.1UF
C653
1
2
0.1UF
C652
1
2
0.1UF
C654
1
2
0.1UF
C655
1
2
0.1UF
C657
1
2
22UF
C658
1
2
22UF
C651
1
2
0.1UF
C669
1
2
0.1UF
C664
1
2
0.1UF
C667
1
2
0.1UF
C663
1
2
0.1UF
C668
1
2
0.1UF
C666
1
2
0.1UF
C665
1
2
22UF
C670
1
2
22UF
C662
1
2
Main Board Electric Diagram: DDR2 BANK-1
45
harman/kardon
BDP 1 / BDP 10 Service Manual
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