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D DR0_A10
D DR0_A9
D DR0_A8
D DR0_A7
D DR0_A6
D DR0_A5
D DR0_A4
D DR0_A3
D DR0_A2
DDR0_CLK1N
DDR0_CLK1
DDR0_CLK0
DDR0_CLK0N
DDR0_D[23:16]
DDR0_D21
DDR0_D17
DDR0_D18
DDR0_D23
DDR0_D16
DDR0_D22
DDR0_D19
DDR0_D20
DDR0_D0
DDR0_D6
DDR0_D5
DDR0_D7
DDR0_D3
DDR0_D2
DDR0_D4
DDR0_D1
+VREF_DDR
DDR0_DQM2
DDR0_DQM3
DDR0_DQS2N
DDR0_DQS2P
DDR0_DQS3N
DDR0_DQS3P
DDR0_ODT23
DDR0_WEN
DDR0_CASN
DDR0_RASN
DDR0_CS1N
D DR0_CKE
DDR0_CLK1N
DDR0_CLK1
DD R0_BA0
DD R0_BA1
DD R0_BA2
DD R0_BA2
DD R0_BA1
DD R0_BA0
D DR0_CKE
DDR0_CS0N
DDR0_RASN
DDR0_CASN
DDR0_WEN
DDR0_ODT01
DDR0_DQS1P
DDR0_DQS1N
DDR0_DQS0P
DDR0_DQS0N
DDR0_DQM1
DDR0_DQM0
DDR0_CLK0
DDR0_D15
DDR0_D11
DDR0_D12
DDR0_D10
DDR0_D13
DDR0_D[15:8]
DDR0_D8
DDR0_D14
DDR0_D9
DDR0_D29
DDR0_D28
DDR0_D31
DDR0_D25
DDR0_D30
DDR0_D26
DDR0_D24
DDR0_D[31:24]
DDR0_D27
+VREF_DDR
D DR0_A13
D DR0_A11
D DR0_A10
D DR0_A9
D DR0_A8
D DR0_A7
D DR0_A6
D DR0_A5
D DR0_A4
D DR0_A3
D DR0_A1
D DR0_A0
D DR0_A12
D DR0_A2
DDR0_CLK0N
D DR0_A11
D DR0_A12
D DR0_A13
D DR0_A[13:0]
D DR0_A1
D DR0_A0
GND
GND
GND
GND
+1V8
+1V8
DDR0_BA2
DDR0_BA1
DDR0_BA0
DDR0_CLK1
DDR0_CLK1N
DDR0_CLK0
DDR0_CLK0N
DDR0_CKE
DDR0_CS1N
DDR0_CS0N
DDR0_RASN
DDR0_DQS3P
DDR0_DQS3N
DDR0_DQS2P
DDR0_DQS2N
DDR0_DQS1P
DDR0_DQS1N
DDR0_DQS0P
DDR0_DQS0N
DDR0_DQM3
DDR0_DQM2
DDR0_DQM1
DDR0_CASN
DDR0_WEN
DDR0_ODT23
DDR0_ODT01
DDR0_DQM0
+VREF_DDR
DDR0_A[13:0]
DDR0_D[15:8]
DDR0_D[7:0]
DDR0_A[13:0]
DDR0_D[31:24]
DDR0_D[23:16]
(CLUSTER)
(CLUSTER)
DDR2 BANK-0
DDR2-0L
DDR2-0H
5- DDR2 clock and DQS P/N traces must be routed as 100 Ohms Differential pairs. Traces width and gap according to PCB stackup.
4- Length of all Data signals between Byte Lane should be matched together (<400 mils).
BCM7440 DDR2 2x16 --> Design notes and Layout Guidelines:
1- Place 121 ohms clock termination at the end of the differencial trace.
2- Pin swaping can only be done on data lines inside each group of 8 bit (Byte Lane).
3- Length of all Data signals into a Byte Lane should be matched together (<100 mils).
1- Place 121 ohms clock termination at the end of the differencial trace.
2- Pin swaping can only be done on data lines inside each group of 8 bit (Byte Lane).
3- Length of all Data signals into a Byte Lane should be matched together (<100 mils).
6- When developing the PCB floor plan, the proximity of the DDR2 device to the memory controller is an important factor.
- To avoid the use of external address termination on high-speed DDR2, the address trace length should be less than 2.5in.
* If those requirements can not be reached, refer to JEDEC JESD79-2B standard for design rules and terminations.
* If those requirements can not be reached, refer to JEDEC JESD79-2B standard for design rules and terminations.
121
R558
2
1
0.1UF
C635
1
2
0.1UF
C630
1
2
0.1UF
C633
1
2
0.1UF
C643
1
2
0.1UF
C632
1
2
DDR2
32Mx16
FBGA 84
HYB18TC1G160CF-2.5
U13
BGA84
NC2
E2
NC1
A2
WE*
K3
VDD5
J9
VDD4
R1
VDD3
M9
VDD2
E1
VDD1
A1
VDDQ10
G9
VDDQ9
G7
VDDQ8
G1
VDDQ7
E9
VDDQ6
G3
VDDQ5
C9
VDDQ4
C7
VDDQ3
C3
VDDQ2
C1
VDDQ1
A9
VDDL
J1
A12
R2
A11
P7
RFU/A13
R8
A10/AP
M2
A9
P3
A8
P8
A7
P2
A6
N7
A5
N3
A4
N8
A3
N2
A2
M7
A1
M3
A0
M8
BA2
L1
BA1
L3
BA0
L2
CK
J8
CK*
K8
VREF
J2
CKE
K2
CS*
L8
RAS*
K7
CAS*
L7
ODT
K9
DQ15
B9
DQ14
B1
DQ13
D9
DQ12
D1
DQ11
D3
DQ10
D7
DQ9
C2
DQ8
C8
DQ7
F9
DQ6
F1
DQ5
H9
DQ4
H1
DQ3
H3
DQ2
H7
DQ1
G2
DQ0
G8
UDM
B3
LDM
F3
UDQS
B7
UDQS*/NU
A8
LDQS
F7
LDQS*/NU
E8
VSS5
P9
VSS4
N1
VSS3
J3
VSS2
E3
VSS1
A3
VSSQ10
H8
VSSQ9
H2
VSSQ8
F8
VSSQ7
F2
VSSQ6
E7
VSSQ5
D8
VSSQ4
D2
VSSQ3
B8
VSSQ2
B2
VSSQ1
A7
VSSDL
J7
RFU/A14
R3
RFU/A15
R7
0.1UF
C644
1
2
DDR2
32Mx16
FBGA 84
HYB18TC1G160CF-2.5
U10
BGA84
NC2
E2
NC1
A2
WE*
K3
VDD5
J9
VDD4
R1
VDD3
M9
VDD2
E1
VDD1
A1
VDDQ10
G9
VDDQ9
G7
VDDQ8
G1
VDDQ7
E9
VDDQ6
G3
VDDQ5
C9
VDDQ4
C7
VDDQ3
C3
VDDQ2
C1
VDDQ1
A9
VDDL
J1
A12
R2
A11
P7
RFU/A13
R8
A10/AP
M2
A9
P3
A8
P8
A7
P2
A6
N7
A5
N3
A4
N8
A3
N2
A2
M7
A1
M3
A0
M8
BA2
L1
BA1
L3
BA0
L2
CK
J8
CK*
K8
VREF
J2
CKE
K2
CS*
L8
RAS*
K7
CAS*
L7
ODT
K9
DQ15
B9
DQ14
B1
DQ13
D9
DQ12
D1
DQ11
D3
DQ10
D7
DQ9
C2
DQ8
C8
DQ7
F9
DQ6
F1
DQ5
H9
DQ4
H1
DQ3
H3
DQ2
H7
DQ1
G2
DQ0
G8
UDM
B3
LDM
F3
UDQS
B7
UDQS*/NU
A8
LDQS
F7
LDQS*/NU
E8
VSS5
P9
VSS4
N1
VSS3
J3
VSS2
E3
VSS1
A3
VSSQ10
H8
VSSQ9
H2
VSSQ8
F8
VSSQ7
F2
VSSQ6
E7
VSSQ5
D8
VSSQ4
D2
VSSQ3
B8
VSSQ2
B2
VSSQ1
A7
VSSDL
J7
RFU/A14
R3
RFU/A15
R7
0.1UF
C631
1
2
22UF
C642
1
2
22UF
C645
1
2
121
R557
2
1
0.1UF
C600
1
2
0.1UF
C599
1
2
0.1UF
C638
1
2
0.1UF
C637
1
2
0.1UF
C605
1
2
0.1UF
C639
1
2
0.1UF
C598
1
2
22UF
C640
1
2
22UF
C604
1
2
Main Board Electric Diagram:DDR2 BANK-0
44
harman/kardon
BDP 1 / BDP 10 Service Manual
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