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Q
R
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X
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AA
FE_FOEB
005:7G;009:D1
FE_NWPB
007:5G
FE_NRBB
007:9F
FE_FWEB
005:7G;009:B10;009:D1
FE_NALE
005:7G
FE_NCLE
005:7G
FE_FCS0B
005:7G
10k
R7300
10k
R7306
XX
R7309
XX
R7311
10k
R7315
R7321
1
0
k
10k
R7317
10k
R7319
XX
R7323
*R7325
1
0
k
XX
R7327
R7334
1
0
k
XX
R7336
XX
R7301
XX
R7335
10k
R7310
XX
R7316
R7333
1
0
k
R7322
X
X
R7337
1
0
k
10k
R7324
10k
R7328
*R7326
X
X
R7312
1
0
k
XX
R7307
XX
R7318
XX
R7320
FE_CI_TSD[0-7],FE_RDAT[0-7]
CL7303
2.5mm
CL7302
2.5mm
FE_FWEB
005:10H;009:B10;009:D1
FE_FOEB
005:10G;009:D1
FE_CI_WAITB
009:D3
XX
R7314
470
R7313
10k
R7302
10k
R7305
10k
R7329
10k
R7330
10k
R7331
1608
10V
1
C7301
470
R7338
10k
R7308
R7303
XX
R7304
XX
FE_RSTB
003:7D;008:8D
FE_3.3V
FE_3.3V
FE_3.3V
H;007:14H;007:15H;007:16D;008:4D;009:B7
47
RB7305
1
FE_CI_CE1B009:B10;009:D1
FE_FCS0B
005:10G
XX
R7332
10k
R7339
XX
R7340
JL7300
JL7301
470
R7341
25V
0 . 0 1
X7R
C7300
25V
0 . 0 1
X7R
C7302
47
RB7306
FE_NALE
005:10H
FE_NCLE
005:10H
FE__NALE
007:9F
FE__NCLE
007:9F
47
RB7302
1
47
RB7300
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
47
RB7301
2
1
4
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6
5
8
7
10
9
12
11
14
13
16
15
47
RB7303
2
1
4
3
6
5
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7
10
9
12
11
14
13
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15
47
RB7304
2
1
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K9F1208U0C-PCB0T
*IC7300
PWB LAYOUT NOTE:
Place NAND-FLASH with consideration
for changing from TSOP to FBGA package
Place NAND-FLASH with consideration
for changing from TSOP to FBGA package
N.C
N.C
N.C
N.C
N.C
N.C
RY_BY
RE
CE
N.C
N.C
VCC
GND
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
IO1
IO2
IO3
IO4
N.C
N.C
N.C
GND
VCC
N.C
N.C
N.C
IO5
IO6
IO7
IO8
N.C
N.C
N.C
N.C
UPD61300F1-230-LU2-A
IC7000
RADD0
AE5
RADD1
AF4
RADD2
AG4
RADD3
AH4
RADD4
AJ3
RADD5
AH3
RADD6
AJ2
RADD7
AH2
RADD8
AJ1
RADD9
AH1
RADD10
AG2
RADD11
AG1
RADD12
AF3
RADD13
AF2
RADD14
AF1
HSDCLK/RADD15
AE4
HSDE/RADD16
AE3
PKTSTRT/RADD17
AE2
HSD0/RADD18
AD5
HSD1/RADD19
AD4
HSD2/RADD20
AD2
HSD3/RADD21
AD1
HSD4/RADD22
AC4
HSD5/RADD23
AC3
HSD6/RADD24
AC2
HSD7/RADD25
AC1
RDATA0
AB4
RDATA1
AB3
RDATA2
AB2
RDATA3
AA5
RDATA4
AA4
RDATA5
AA2
RDATA6
AA1
RDATA7
Y4
STP0DATA0/RDATA8
Y3
STP0DATA1/RDATA9
Y2
STP0DATA2/RDATA10
Y1
STP0DATA3/RDATA11
W5
STP0DATA4/RDATA12
W4
STP0DATA5/RDATA13
W3
STP0DATA6/RDATA14
W2
STP0DATA7/RDATA15
W1
FOEB
AF5
FWEB
AH6
FCSB0
AJ5
FCSB1
AJ6
GCSB0
AH5
GCSB1
AG5
GRDY
AG6
FE_RDAT[7]
FE_RDAT[6]
FE_RDAT[5]
FE_RDAT[4]
FE_RDAT[3]
FE_RDAT[2]
FE_RDAT[1]
FE_RDAT[0]
FE_CI_TSD[0-7],FE_RD
A
T[0-7]
FE_RADD[0]
FE_RADD[1]
FE_RADD[2]
FE_RADD[3]
FE_RADD[4]
FE_RADD[5]
FE_RADD[6]
FE_RADD[9]
FE_RADD[10]
FE_RADD[11]
FE_RADD[14]
FE_RADD[15]
FE_RADD[16]
FE_RADD[17]
FE_RADD[18]
FE_RADD[12]
FE__RADD[0]
FE__RADD[1]
FE__RADD[2]
FE__RADD[3]
FE__RADD[7]
FE__RADD[4]
FE__RADD[6]
FE__RADD[5]
FE__RADD[12]
FE__RADD[14]
FE__RADD[11]
FE__RADD[15]
FE__RADD[13]
FE__RADD[8]
FE__RADD[10]
FE__RADD[9]
FE__RADD[19]
FE__RADD[16]
FE__RADD[18]
FE__RADD[17]
FE__RDAT[4]
FE__RDAT[6]
FE__RDAT[3]
FE__RDAT[7]
FE__RDAT[5]
FE__RDAT[0]
FE__RDAT[2]
FE__RDAT[1]
FE__RDAT[12]
FE__RDAT[14]
FE__RDAT[11]
FE__RDAT[15]
FE__RDAT[13]
FE__RDAT[8]
FE__RDAT[10]
FE__RDAT[9]
FE__GCS0B
FE__FOEB
FE__FCS0B
FE__FWEB
FE__RADD[18]
FE_RADD[19]
FE__FWEB
FE__FOEB
FE__RADD[19]
FE_RADD[18]
FE_CI_TSD[1]
FE_RDAT[0]
FE__RDAT[0]
FE__RDAT[13]
FE__RDAT[7]
FE__RDAT[11]
FE__RDAT[4]
FE_RDAT[4]
FE_RDAT[2]
FE_CI_TSD[7]
FE_RDAT[6]
FE_RDAT[1]
FE__RDAT[12]
FE_CI_TSD[3]
FE__RDAT[3]
FE__RDAT[10]
FE_CI_TSD[0]
FE_RDAT[5]
FE_CI_TSD[2]
FE_RDAT[3]
FE__RDAT[8]
FE__RDAT[5]
FE_CI_TSD[5]
FE__RDAT[9]
FE__RDAT[2]
FE__RDAT[15]
FE_CI_TSD[4]
FE__RDAT[14]
FE_CI_TSD[6]
FE__RDAT[1]
FE__RDAT[6]
FE_RDAT[7]
FE__RADD[4]
FE__RADD[16]
FE__RADD[11]
FE_RADD[14]
FE__RADD[2]
FE__RADD[7]
FE_RADD[3]
FE__RADD[9]
FE_RADD[1]
FE__RADD[17]
FE__RADD[5]
FE__RADD[0]
FE__RADD[15]
FE_RADD[16]
FE_RADD[6]
FE_RADD[5]
FE_RADD[4]
FE__RADD[12]
FE__RADD[13]
FE__RADD[6]
FE_RADD[15]
FE_RADD[12]
FE__RADD[8]
FE_RADD[17]
FE_RADD[13]
FE_RADD[8]
FE_RADD[11]
FE_RADD[2]
FE_RADD[0]
FE_RADD[9]
FE_RADD[7]
FE__RADD[10]
FE__RADD[3]
FE_RADD[10]
FE__RADD[14]
FE__RADD[1]
FE__FCS0B
FE__GCS0B
FE_RADD[13]
FE_RADD[19]
FE_RADD[7]
FE_RADD[8]
R A D D [ 0 ] = C P U _ E N D I A N = 1 = B i g
R A D D [ 1 ] = t e s t = 0
R A D D [ 2 ] = t e s t = 0
RADD[ 4: 3] = CPUCLK_SEL[1:0] = 01 = 262.144MHz
R A D D [ 5 ] = M C L K _ S E L = 0 = 3 2 7 . 6 8 0 M H z
R A D D [ 6 ] = RO M _ E N D I A N = 1 = B i g
R A D D [ 7 ] = RO M _ B W S E L = 1 = 8 - b i t
RADD[10: 8] = BOOT_MODE[2:0] = 011 = NAND, then MS
RADD[12:11] = BOOT_NAND_SEL[1:0] = 01 = =>512Mb 00 = <=256MB
R A D D [ 1 3 ] = N A N D _ C S = 0 = C S 0
R A D D [ 1 4 ] = t e s t = 0
R A D D [ 1 5 ] = t e s t = 0
R A D D [ 1 6 ] = t e s t = 0
RADD[17] = EJTAG_MODE = 1 = EJTAG
R A D D [ 1 8 ] = D I N T _ E N = 0 = D i s a b l e
R A D D [ 1 9 ] = D S Y S E L B = 1 = O n l y M a i n C P U
R A D D [ 1 ] = t e s t = 0
R A D D [ 2 ] = t e s t = 0
RADD[ 4: 3] = CPUCLK_SEL[1:0] = 01 = 262.144MHz
R A D D [ 5 ] = M C L K _ S E L = 0 = 3 2 7 . 6 8 0 M H z
R A D D [ 6 ] = RO M _ E N D I A N = 1 = B i g
R A D D [ 7 ] = RO M _ B W S E L = 1 = 8 - b i t
RADD[10: 8] = BOOT_MODE[2:0] = 011 = NAND, then MS
RADD[12:11] = BOOT_NAND_SEL[1:0] = 01 = =>512Mb 00 = <=256MB
R A D D [ 1 3 ] = N A N D _ C S = 0 = C S 0
R A D D [ 1 4 ] = t e s t = 0
R A D D [ 1 5 ] = t e s t = 0
R A D D [ 1 6 ] = t e s t = 0
RADD[17] = EJTAG_MODE = 1 = EJTAG
R A D D [ 1 8 ] = D I N T _ E N = 0 = D i s a b l e
R A D D [ 1 9 ] = D S Y S E L B = 1 = O n l y M a i n C P U
STRAP SETTINGS
STRAP SETTINGS
PWB LAYOUT NOTE:
P i n - swa p a l l owe d o n
t h e s e r e s i s t o r a r r a y s
fo r o p t i m a l P W B l ayo u t
P i n - swa p a l l owe d o n
t h e s e r e s i s t o r a r r a y s
fo r o p t i m a l P W B l ayo u t
To fo r c e B o o t f r o m M S :
c o n n e c t ( s h o r t ) t o g e t h e r
CL7302 & CL.7303
P l a c e C L s t o g e t h e r a n d
i n a c c e s s i b l e l o c a t i o n
c o n n e c t ( s h o r t ) t o g e t h e r
CL7302 & CL.7303
P l a c e C L s t o g e t h e r a n d
i n a c c e s s i b l e l o c a t i o n
PWB LAYOUT NOTE:
P l a c e f i t t e d s t r a p r e s i s t o r s i n g r o u p s
o f 4 o r 8 t o a l l o w r e p l a c e m e n t b y
r e s i s t o r a r r a y s d u r i n g l a t e r t r i a l
P l a c e f i t t e d s t r a p r e s i s t o r s i n g r o u p s
o f 4 o r 8 t o a l l o w r e p l a c e m e n t b y
r e s i s t o r a r r a y s d u r i n g l a t e r t r i a l
BGE
3/22
BGE - EG1L
COMPONENTS MARKED AS XX REFER TO PARTS LIST, WILL ONLY BE LISTED IF FITTED
FE_RADD[0-14]
~ BGE Board Schematic Diagram [ Main Microcontroller, HDMI/AV Side/PC Input, Audio Processor, Scarts ] Page 3/22 ~
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