Read Sony RM-PJVW100 / VPL-VW100 Service Manual online
5-8
VPL-VW100
5-8
Q (3/6)
Q (3/6)
Q(3/6)
IC1100
DRC
IC2300
DRC FPGA
4/6
DRC SW2
DRC SW3
B13,A13
50,51,54,56-60
41-44,46-49
64
63
62
DRC Y[0-7]
DRC C[0-7]
DBO0
|
DBO1
DRC Y[0]
|
DRC Y[7]
DRC C[0]
|
DRC C[7]
DRC HS
DRC VS
DRC CLK
DBO2
|
DBO9
DYO2
|
DYO5
DYO6
|
DYO9
DB[0-1]
DB[2-9]
DY[2-5]
DY[6-9]
DR[2-3]
DR[4-9]
HDO
VDO
CKCO
C9
C8
A9
D12,C12,B12,
D11,C11,B11,
A11,B10
D11,C11,B11,
A11,B10
A19,D18,
C18,B18
C18,B18
A18,C17,
B17,A17
B17,A17
D15,C15
B15,A15,C14,
B14,A14,C13
B14,A14,C13
GFBK
GHS
GVS
GCLK
2
8
4
8
4
2
6
2
8
4
4
2
6
3-2
9-2
7-4
1,19
17-18
11-18
13-16
11-14
IC1105
1,19
IC1104
1,19
IC1107
9-6
IC1106
1,19
3-2
1,19
17-18
IC1106
9-4
1,19
11-16
IC1105
2
3
4
6
18
17
16
14
1,19
IC1103
BUFF
BE[0-1]
BE[2-9]
GE[2-5]
DYO0
|
DYO1
DY[0-1]
C19,B19
2
2
9-8
11-12
1,19
IC1107
GE[0-1]
GE[6-9]
GE[2-9]
8 RE[2-9]
RE[2-3]
RE[4-9]
DRO2
|
DRO3
DR[0-1]
C16,B16
2
2
5-4
1,19
15-16
IC1106
RE[0-1]
DRO0
|
DRO1
DRO4
|
DRO9
2
4
IC1102
U2,U3,V1-V3,
W2-W4
R2-R4,
T1-T4,U1
P3
P2
R1
G25
K25
DIYD0
|
DIYD7
|
DIYD7
DICD0
|
DICD7
|
DICD7
IHDD
IVDD
CKDI
DRC HS
DRC VS
DRC CLK
CKCI
CKBI
8
8
8
8
8
X2
1
5
4
X1
CLK2
CLK1
X1300
16.384MHz
CLOCK GEN
IC1108
2,4,5,7,8,10,11,13,
74,76,77,79,80,82,83,85,
31,33,34,36,37,39,40,42,
45,47,48,50,51,53,54,56
74,76,77,79,80,82,83,85,
31,33,34,36,37,39,40,42,
45,47,48,50,51,53,54,56
25-27,60-66,24
22
23
19
18
17
20
68
2
3
4
5
6
7
10
1
9
BA0
BA1
RAS#
CAS#
WE#
CS#
CLK
SW0
DAC4
DAC3
DAC2
DAC1
DAC0
SW3
SW1
SW2
IC1109
SDRAM
DQ000
|
DQ031
|
DQ031
AD000
|
AD010
|
AD010
AD100
|
AD110
|
AD110
DQ0
|
DQ31
A0
|
A10
AC1,AD1,AE1,AC1,AD2,AF2,AC3,AE3,
AD7,AE7,AC6,AD6,AE6,AF6,AE5,AF5,
AE16,AD16,AC16,AF17,AE17,AD17,AF18,AE18,
AD13,AE13,AF13,AC12,AD12,AE12,AC11,AD11
AD13,AE13,AF13,AC12,AD12,AE12,AC11,AD11
AE15,AD15,AC15,
AF11,AD10,AE10,AF10,
AD9,AE9,AC8,AD14,
A0[0-10]
IC2302
D/A CONVERTER
D0[0-31]
BA00
BA01
XRAS0
XCAS0
XWE0
XCS0
SDCK0
AE14
AF14
AF4
AE4
AD4
AD5
AF8
B0 0
B0 1
RAS0
CAS0
WE0
CS 0
CK0
2,4,5,7,8,10,11,13,
74,76,77,79,80,82,83,85,
31,33,34,36,37,39,40,42,
45,47,48,50,51,53,54,56
74,76,77,79,80,82,83,85,
31,33,34,36,37,39,40,42,
45,47,48,50,51,53,54,56
25-27,60-66,24
22
23
19
18
17
20
68
BA0
BA1
RAS#
CAS#
WE#
CS#
CLK
IC1110
SDRAM
DQ100
|
DQ131
|
DQ131
DQ0
|
DQ31
A0
|
A10
AD20,AE20,AF20,AC21,AD21,AE21,AF21,AC22,
AC25,AC26,AD25,AD26,AE26,AF25,AE24,AF24,
AC25,AC26,AD25,AD26,AE26,AF25,AE24,AF24,
P24,P23,N26,N25,N24,N23,M25,M24,
T26,U24,U25,U26,V23,V24,V25,W24
R25,R24,R23,W26,
Y24,Y25,Y26,AA24,
AA25,AB23,R26
A1[0-10]
D1[0-31]
BA10
BA11
XRAS1
XCAS1
XWE1
XCS1
SDCK1
T24
T25
AE23
AD23
AE22
AF23
AB26
B1 0
B1 1
RAS1
CAS1
WE1
CS 1
CK1
6/6
6/6
SDA 400K
SCL 400K
E26
E25
SDATA
SCLK
XRST
E23
DRC RESET 2
D3.3V
1.8V
1.8V
REG
REG
IC1101
BEI[2]
|
BEI[9]
|
BEI[9]
GEI[2]
|
GEI[9]
|
GEI[9]
REI[2]
|
REI[9]
|
REI[9]
132-129,
126,124-122
8
141-136,
134,133
8
13-10,7-4
8
FBKI
VSI
CLKI
21
20
15,18
GFBK
GVS
GCLK
V POL
H POL
SYS STOP
DVI EN
MODE2
HDLY
CHROMA
D0
CCLK
PROGRAM
INIT
DONE
TDO
TDI
TMS
TCK
SDA
SCL
87
83
80
79
78
76
74
34
32
142
2
4
5
6
14
15
DRC RESET 2
6/6
6/6
SDA 100K
SCL 100K
Q2300
1
3
7
8
10
17
D0
CLK
CF
OE/RESET
CE
TDO
IC2301
FPGA ROM
TDI
TMS
TCK
39
37
69
68
72
D3.3V
D3.3V
CN2300
VCC
TDO
TDI
TMS
TCK
1
3
4
5
6
BE[2-9]
4/6
BE[0-1]
4/6
GE[2-9]
4/6
GE[0-1]
4/6
RE[2-9]
4/6
4/6
4/6
4/6
4/6
RE[0-1]
4/6
BEI[2-9]
1/6, 2/6
GEI[2-9]
1/6, 2/6
REI[2-9]
1/6, 2/6
FBKI
VSI
CLKI
1/6, 2/6
1/6, 2/6
1/6, 2/6
1/6, 2/6
DRC SW 2
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