Read Sony DVP-NS9100ES Service Manual online
111
DVP-NS9100ES
Pin No.
Pin Name
I/O
Description
118, 119
MCIF_DATA14,
MCIF_DATA15
I/O
Two-way data bus with the flash memory and i.link system controller
120 to 129
MCIF_ADDR1 to
MCIF_ADDR10
I
Address signal input from the i.link system controller
130
VDD
-
Power supply terminal (+3.3V)
131
VSS
-
Ground terminal
132
MCIF ENDIAN
I
Endian setting terminal for interface
"L": big endian, "H": little endian Fixed at "L" this set
"L": big endian, "H": little endian Fixed at "L" this set
133 to 135
MCIF_MODE0 to
MCIF_MODE2
I
CPU operation mode setting terminal
136
HSDI0_60958_IN
I
60958 data input terminal Not used
137
HSDI0_
AMCLK_IN
I
Audio master clock signal input terminal Not used
138
HSDI0_CLK
I
Clock signal input terminal Not used
139
HSDI0_EN
I
Data enable signal input terminal Not used
140
HSDI0_AV
O
Not used
141
HSDI0_SYNC
O
SYNC signal output terminal Not used
142
HSDI0_DVALID
O
Not used
143, 144
HSDI0_D0,
HSDI0_D1
I/O
Data input/output terminal Not used
145
VDD
-
Power supply terminal (+3.3V)
146
VSS
-
Ground terminal
147 to 152
HSDI0_D2 to
HSDI0_D7
I/O
Data input/output terminal Not used
153
HSDI1_CLK
I
DSD clock signal input from the i.link DSP
154
HSDI1_EN
I
Data enable signal input terminal Not used
155
HSDI1_AV
O
Not used
156
HSDI1_SYNC
I
Frame signal input from the i.link DSP
157
HSDI1_DVALID
O
Not used
158
HSDI1_D0
I
DSD data (for front L-ch) input from the i.link DSP
159
HSDI1_D1
I
DSD data (for front R-ch) input from the i.link DSP
160
REG_OUT
O
+1.8V power supply output terminal
161
VDD
-
Power supply terminal (+3.3V)
162
VSS
-
Ground terminal
163
HSDI1_D2
I
DSD data (for center) input from the i.link DSP
164
HSDI1_D3
I
DSD data (for woofer) input from the i.link DSP
165
HSDI1_D4
I
DSD data (for rear L-ch) input from the i.link DSP
166
HSDI1_D5
I
DSD data (for rear R-ch) input from the i.link DSP
167
HSDI1_D6
I
Ancillary signal input from the i.link DSP
168
HSDI1_D7
I/O
Data input/output terminal Not used
169
HSDI1_
AMCLK_IN
I
Audio master clock signal input from clock generator
170
HSDI1_
AMCLK_OUT
O
Audio master clock signal output terminal Not used
171
HSDI1_
AMCLK_ERR
O
Audio error signal output terminal Not used
172
HSDI1_
AMCLK_MUTE
O
Audio muting on/off control signal output terminal Not used
173
HSDI1_60958_IN
I
Digital audio data input from the lip sync adjust
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