MDX-C8970R - Sony Car Audio Service Manual (repair manual). Page 65

65

Pin No.

Pin Name

I/O

Description

63

SP-SCK

I

Spectrum analyzer display serial data transfer clock signal input from the master controller 
(IC500)

64

LCDCLK

O

Display serial data transfer clock signal output to the liquid crystal display driver (IC900, 920)

65

VSS

—

Ground terminal

66

LCDINH

O

Blank indicate control signal output to the liquid crystal display driver (IC900, 920)
“L”: no display

67, 68

VSS

—

Ground terminal

69

LCDCE0

O

Chip enable signal output to the liquid crystal display driver (IC900)    “H” active

70

LCDCE1

O

Chip enable signal output to the liquid crystal display driver (IC920)    “L” active

71

P63

O

Not used (open)

72 to 78

P27 to P21

O

Not used (open)

79

FL W

O

Flash memory data write control signal output terminal    “H”: active

80

FWE (L)

I

Flash memory data write enable signal input terminal

81

RESET

I

System reset signal input from the reset signal generator (IC506) and reset switch (S703)
“L” is input for several 100 msec after power on, then it changes to “H”

82

NMI (H)

I

Non maskable interrupt input terminal
Connect the backup detect circuit (BU-IN pin $ª) in this set

83

STBY (H)

I

Hard ware standby input terminal      Not used (fixed at  “H”)

84

VCC

—

Power supply terminal (+5V)

85

XTAL

O

System clock output terminal (18.432 MHz)

86

EXTAL

I

System clock input terminal (18.432 MHz)

87

VSS

—

Ground terminal

88

PF7

O

Not used (open)

89

VCC

—

Power supply terminal (+5V)

90 to 96

PF6 to PF0

O

Not used (open)

97

UNI-SO

O

Serial data output to the SONY bus interface (IC271)

98

UNI-SO

I

Serial data input from the SONY bus interface (IC271)

99, 100

VSS

—

Ground terminal

101

UNI-SCK

I/O

Serial clock signal input /output with the MD mechanism controller (IC501) and master controller 
(IC500) or serial clock signal output to the SONY bus interface (IC271)

102

P53/ADTRG

O

Not used (open)

103

AVCC

—

Power supply terminal (+5V) (for A/D converter)

104

VREF

I

Reference voltage (+5V) input terminal (for A/D converter)

105 to 110

P40/AN0 to

P45/AN5

I

Not used (fixed at “L”)

111

P46/AN6/DA0

I

Not used (fixed at “L”)

112

P47/AN7/DA1

I

Not used (fixed at “L”)

113

AVSS

—

Ground terminal (for A/D converter)

114

VSS

—

Ground terminal

115 to 122

P17 to P10

O

Not used (open)

123

MD0 (H)

I

Setting terminal for the CPU operational mode (fixed at “H” in this set)

124

MD1 (H)

I

Setting terminal for the CPU operational mode (fixed at “H” in this set)

125

MD2 (H)

I

Setting terminal for the CPU operational mode (fixed at “H” in this set)

126 to 128

PG0 to PG2

O

Not used (open)