Read Sony CDX-G1000U / CDX-G1000UE / CDX-G1001U / CDX-G1002U / CDX-G1050U / CDX-G1050UE / CDX-G1051U / CDX-G1070U / CDX-G1071U / CDX-G1080UM Service Manual online
CDX-G1000U/G1000UE/G1001U/G1002U/G1050U/G1050UE/G1051U/G1070U/G1071U/G1080UM
30
Pin No.
Pin Name
I/O
Description
64
MECHA SEL
I
CD mechanism deck detection signal input terminal “H”: CD mechanism deck is detected
Fixed at “H” in this unit
Fixed at “H” in this unit
65
GP47 (NCO)
-
Not used
66
DVSS
-
Ground terminal (digital system)
67
DVDD
-
Power supply terminal (+3.3V) (digital system)
68
UDM1
I/O
Two-way USB data (–) bus with the USB connector
69
UDP1
I/O
Two-way USB data (+) bus with the USB connector
70
DVSS
-
Ground terminal (for digital system)
71
UDM2
I/O
Two-way USB data (–) bus terminal Fixed at “L” in this unit
72
UDP2
I/O
Two-way USB data (+) bus terminal Fixed at “L” in this unit
73
XVDD
-
Power supply terminal (+3.3V) (for oscillation circuit)
74
X12IN
I
System clock input terminal (12 MHz)
75
X12OUT
O
System clock output terminal (12 MHz)
76
XVSS
-
Ground terminal (for oscillation circuit)
77
AFILT
O
Charge pump output terminal for PLL
78, 79
VVDD2, VVDD3
-
Power supply terminal (+3.3V) (for PLL)
80
DVSS
-
Ground terminal (digital system)
81
DVDD
-
Power supply terminal (+3.3V) (digital system)
82
CP_SCL
O
Serial data transfer clock signal output terminal Not used
83
CP_SDA
I/O
Two-way data bus terminal Not used
84
CP_RESET
O
Reset signal output terminal Not used
85
CD_RESB
I
Reset signal input from the digital servo processor “L”: reset
86
CMD_ERR
O
Command error signal output to the system controller “H”: error
87
TEST0 (GND)
I
Test mode setting terminal Fixed at “L”
88
DVDD
-
Power supply terminal (+3.3V) (digital system)
89
DVSS
-
Ground terminal (for digital system)
90
DVDD15
-
External capacitor connection terminal for internal regulator
91
JTRSTB (IPD)
I
Reset signal input terminal (for JTAG) Normally: fi xed at “L”
92
JTCK (IPD)
I
Clock signal input terminal (for JTAG) Normally: fi xed at “L”
93
JTDI (IPD)
I
Data input terminal (for JTAG) Normally: fi xed at “L”
94
JTMS (IPU)
I
Mode selection signal input terminal (for JTAG) Normally: fi xed at “H”
95
JTDO (O)
O
Data output terminal (for JTAG) Normally: open
96
JTRTCK (O)
O
Return clock signal output terminal (for JTAG) Normally: open
97
TEST1 (GND)
I
Test mode setting terminal Fixed at “L”
98
AVDD1
-
Power supply terminal (+3.3V) (analog system)
99
AVSS1
-
Ground terminal (analog system)
100
LRREF
-
External capacitor connection terminal for audio D/A converter and electrical volume reference
voltage
voltage
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