Read Sony ZS-M30 Service Manual online
31
ZS-M30
• MD BOARD IC 504 CXD2654R
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO SIGNAL PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
1
MNT0 (FOK)
O
Focus OK signal output to the MD mechanism controller (IC601)
“H” is output when focus is on (“L”: NG)
2
MNT1 (SHOCK)
O
Track jump detection signal output to the MD mechanism controller (IC601)
3
MNT2 (XBUSY)
O
Busy monitor signal output to the MD mechanism controller (IC601)
4
MNT3 (SLOCK)
O
Spindle servo lock status monitor signal output to the MD mechanism controller (IC601)
5
SWDT
I
Writing serial data signal input from the MD mechanism controller (IC601)
6
SCLK
I (S) Serial data transfer clock signal input from the MD mechanism controller (IC601)
7
XLAT
I (S) Serial data latch pulse signal input from the MD mechanism controller (IC601)
8
SRDT
O (3) Reading serial data signal output to the MD mechanism controller (IC601)
9
SENS
O (3) Internal status (SENSE) output to the MD mechanism controller (IC601)
10
XRST
I (S) Reset signal input from the MD mechanism controller (IC601) “L”: reset
11
SQSY
O
Subcode Q sync (SCOR) output to the MD mechanism controller (IC601)
“L” is output every 13.3 msec Almost all, “H” is output
12
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output to the MD mechanism
controller(IC601) “L” is output every 13.3 msec Almost all, “H” is output
13
RECP
I
Laser power selection signal input from the MD mechanism controller (IC601)“L”:
playback mode, “H”: recording mode
14
XINT
O
Interrupt status output to the MD mechanism controller (IC601)
15
TX
I
Recording data output enable signal input from the MD mechanism controller(IC601)
Writing data transmission timing input (Also serves as the magnetic head on/off output)
16
OSCI
I
System clock signal (512 Fs = 45.1584 MHz) input terminal
17
OSCO
O
System clock signal (512 Fs = 45.1584 MHz) output terminal
18
XTSL
I
Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
19
DIN0
I
Digital audio signal input terminal when recording mode (for digital optical input) Not
used
20
DIN1
I
Digital audio signal input terminal when recording mode (for digital optical input)
21
DOUT
O
Digital audio signal output terminal when playback mode (for digital optical output)
Not used
22
DATAI
I
Serial data input terminal Not used (fixed at “L”)
23
LRCKI
I
L/R sampling clock signal (44.1 kHz) input terminal Not used (fixed at “L”)
24
XBCKI
I
Bit clock signal (2.8224 MHz) input terminal Not used (fixed at “L”)
25
ADDT
I
Recording data input from the A/D, D/A converter (IC604)
26
DADI
I
Playback data input from the A/D, D/A converter (IC604)
27
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the A/D, D/A converter (IC604)
28
XBCK
O
Bit clock signal (2.8224 MHz) output to the A/D, D/A converter (IC604)
29
FS256
O
Clock signal (11.2896 MHz) output terminal
30
DVDD
—
Power supply terminal (+3.3 V) (digital system)
31 – 34
A03
O
A00 O Address signal output to the D-RAM (IC505)
35
A10
O
Address signal output to the external D-RAM Not used (open)
36 – 40
A04 – A08
O
Address signal output to the D-RAM (IC505)
41
A11
O
Address signal output to the external D-RAM Not used (open)
42
DVSS
—
Ground terminal (digital system)
43
XOE
O
Output enable signal output to the D-RAM (IC505) “L” active
44
XCAS
O
Column address strobe signal output to the D-RAM (IC505) “L” active
45
A09
O
Address signal output to the D-RAM (IC505)
Pin No.
Pin Name
I/O
Pin Description
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