Read Sony STR-DA6400ES (serv.man4) Service Manual online
37
FIELD PROGRAMMABLE GATE ARRAY (FPGA, IC2003) is used
for H.A.T.S. operation. When FPGA (IC2003) boots up by reset signal
from SYSTEM CONTROL (IC2513 27pin), FPGA starts to read the
operation firmware from FLASH MEMORY (IC2004).
from SYSTEM CONTROL (IC2513 27pin), FPGA starts to read the
operation firmware from FLASH MEMORY (IC2004).
The operation clock of FPGA is 22.5792MHz(X2001). 24MHz which is
sampled from SPDIF signal in HDMI signal is input to FPGA (IC2003
22pin) through CLOCK SELECT (IC2005). This 24MHz is used for
adjusting data output timing when H.A.T.S. function is ON
22pin) through CLOCK SELECT (IC2005). This 24MHz is used for
adjusting data output timing when H.A.T.S. function is ON
SDO1-3 signals from DSP2 (IC5202) input to FPGA (IC2003). FPGA
adjusts the signal timing with SD-RAM (IC2002) by 24MHz when
H.A.T.S. function is ON.
H.A.T.S. function is ON.
SD0-3OUT signals from FPGA (IC2003) are sent to LIP SYNC
ADJUST (IC2223). By setting of Menu, LIP SYNC ADJUST (IC2223)
adjusts the output data timing with SD-RAM (IC2224).
adjusts the output data timing with SD-RAM (IC2224).
Digital muting signal outputs from SYSTEM CONTROLLER (IC2513
52pin) or FIELD PROGRAMMABLE GATE ARRAY (IC2003 3pin) to
LIP SYNC ADJUST (IC2223 14pin) through MUTING SW (IC2227)
when the muting is necessary for changing mode, etc.
LIP SYNC ADJUST (IC2223 14pin) through MUTING SW (IC2227)
when the muting is necessary for changing mode, etc.
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