STR-DA3200ES, STR-DG1000 - Sony Audio Service Manual (repair manual). Page 121

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121
STR-DA3200ES/DG1000
Pin No.
Pin Name
I/O
Description
84
OVDD
-
Power supply terminal (+3.3V) (for I/O)
85
OVSS
-
Ground terminal (for I/O)
86 to 89
MA1, MA6,
MA0, MA7
O
Address signal output to the SD-RAM
90
OVSS
-
Ground terminal (for I/O)
91
TEST5
-
Ground terminal (for I/O)
92
CVSS
-
Ground terminal (for core)
93
OVDD
-
Power supply terminal (+3.3V) (for I/O)
94 to 97
MA10, MA8,
MA11, MA9
O
Address signal output to the SD-RAM
98
OVDD
-
Power supply terminal (+3.3V) (for I/O)
99
OVSS
-
Ground terminal (for I/O)
100
RAS
O
Row address strobe signal output to the SD-RAM
101
DQM
O
Data mask signal output to the SD-RAM
102
CAS
O
Column address strobe signal output to the SD-RAM
103
MCLK
O
Serial data transfer clock signal output to the SD-RAM
104
WE
O
Write enable signal output to the SD-RAM
105
TEST3
I
Terminal for test    Fixed at "L" in this set
106
TEST4
I
Terminal for test    Fixed at "L" in this set
107
OVSS
-
Ground terminal (for I/O)
108
OVDD
-
Power supply terminal (+3.3V) (for I/O)
109
CVDD
-
Power supply terminal (+2.5V) (for core)
110 to 113
MD7, MD8,
MD6, MD9
I/O
Two-way data bus with the SD-RAM
114
OVDD
-
Power supply terminal (+3.3V) (for I/O)
115
OVSS
-
Ground terminal (for I/O)
116 to 119
MD5, MD10,
MD4, MD11
I/O
Two-way data bus with the SD-RAM
120
OVDD
-
Power supply terminal (+3.3V) (for I/O)
121
OVSS
-
Ground terminal (for I/O)
122 to 125
MD3, MD12,
MD2, MD13
I/O
Two-way data bus with the SD-RAM
126
OVSS
-
Ground terminal (for I/O)
127
CVSS
-
Ground terminal (for core)
128
OVDD
-
Power supply terminal (+3.3V) (for I/O)
129 to 132
MD1, MD14,
MD0, MD15
I/O
Two-way data bus with the SD-RAM
133
SLV
I
MPU interface slave address setting terminal
Slave address setting: 0 x 72 when SLV is "0", 0 x 70 when SLV is "1"
134
RFFO
O
MPEG flag (repeat first field flag) output terminal    Not used
135
SDA
I/O
I2C two-way data bus with the HDMI receiver, HDMI transmitter, HDMI controller, VIDEO A/D
converter and video encoder
136
SCL
I
Serial data transfer clock signal input from the HDMI controller
137
SRN
I
System reset signal input from the HDMI controller    "L": reset
138
OVSS
-
Ground terminal (for I/O)
139
CVDD
-
Power supply terminal (+2.5V) (for core)
140
PLL VDD
-
Power supply terminal (+2.5V) (for PLL)
141
VPDX
-
Not used
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