NW-S4 - Sony Audio Service Manual (repair manual). Page 13

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NW-S4
14
14
3.4 Vp-p
22.7 
µ
s
3.4 Vp-p
710 ns
4.1 Vp-p
3.5 
µ
s
4.1 Vp-p
6.6 
µ
s
3.2 Vp-p
125 ns
1.8 Vp-p
30.5 
µ
s
1.2 Vp-p
59.1 ns
3.2 Vp-p
59.1 ns
3.4 Vp-p
22.7 
µ
s
3.4 Vp-p
710 ns
3 Vp-p
20.8 ns
Note on Printed Wiring Board:
X
: parts extracted from the component side.
Y
: parts extracted from the conductor side.
f
: internal component.
: Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)
Caution:
Pattern face side:
Parts on the pattern face side seen from
(Conductor Side)
the pattern face are indicated.
Parts face side:
Parts on the parts face side seen from
(Component Side)
the parts face are indicated.
4-2.
NOTE  FOR  PRINTED  WIRING  BOARDS  AND  SCHEMATIC  DIAGRAMS
• MAIN and SUB boards are multi-layer printed board.
However, the patterns of intermediate-layer have not been in-
cluded in this diagrams.
Note on Schematic Diagram:
• All capacitors are in 
µ
F unless otherwise noted.  pF: 
µµ
F
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in 
 and 
1
/
4
 
W or less unless otherwise
specified.
%
: indicates tolerance.
f
: internal component.
C
: panel designation.
A
: B+ Line.
• Power voltage is dc 1.5 V and fed with regulated dc power
supply from battery terminal.
• Voltages and waveforms are dc with respect to ground in
playback mode.
no mark : PLAYBACK
: Impossible to measure
• Voltages are taken with a VOM (Input impedance 10 M
).
Voltage variations may be noted due to normal produc-
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
• Signal path.
F
: PLAYBACK
*
The voltage and waveform of CSP (chip size package)
cannot be measured, because its lead layout is different
form that of conventional IC.
• Waveforms
– MAIN Board –
1
IC901 
6
 (XIN) (When power on)
50 mV/DIV, 50 ns/DIV
2
IC601 
rk
 (BCLKX0)
2 V/DIV, 500 ns/DIV
3
IC601 
td
 (BFSX0)
1 V/DIV, 5 
µ
s/DIV
4
IC601 
ua
 (BCLKX1)
2 V/DIV, 50 ns/DIV
5
IC601 
oj
 (X2/CLKIN)
200 mV/DIV, 50 ns/DIV
6
IC801 
2
 (X1)
500 mV/DIV, 20 
µ
s/DIV
7
IC801 
5
 (OSC2) (When power on)
100 mV/DIV, 200 ns/DIV
8
IC401 
7
 (LX)
1 V/DIV, 2 
µ
s/DIV
9
IC404 
9
 (LX)
1 V/DIV, 2 
µ
s/DIV
– SUB Board –
0
IC302 
1
 (LRCK)
1 V/DIV, 5 
µ
s/DIV
qa
IC302 
3
 (SCLK)
2 V/DIV, 500 ns/DIV
qs
IC302 
5
 (MCLK)
2 V/DIV, 50 ns/DIV
3.2 Vp-p
59.1 ns
*
Lead Layouts (IC601 and IC901)
surface
Lead layout of conventional IC
CSP (chip size package)
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