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43
NW-HD3
MAIN BOARD IC7001 CXD1616GH (MULTI INTERFACE)
Pin No.
Pin Name
I/O
Description
1
XTAL
I
Sub system clock input terminal Not used
2
EXTAL
O
Sub system clock output terminal Not used
3
CLK2550A
O
Clock signal (22.5792 MHz) output to the sub system controller
4
CLK2550X
O
Clock signal (22.5792 MHz) inversion output to the sub system controller
5
XOSCSTP
I
Oscillation stop signal input terminal Not used
6
XRESET
I
Reset signal input from the main system controller
7
EXCLKIN
I
Clock signal (176 kHz) input from the main system controller
8 to 30
A1 to A23
I
Address signal input from the main system controller
31 to 46
D0 to D15
I/O
Two-way data bus with the main system controller and flash memory
47 to 49
XCS1 to XCS3
I
Chip select signal input from the main system controller
50
XRD
I
Read signal input from the main system controller
51
XWR
I
Write signal input from the main system controller
52
XLB
I
Write strobe signal input from the main system controller (lower byte)
53
XUB
I
Write strobe signal input from the main system controller (upper byte)
54
XWAIT
I
Wait signal input from the main system controller
55, 56
NC
—
Not used
57
XINTREQG
O
Interrupt request signal output to the main system controller
58
XINTREQH
O
Interrupt request signal output to the main system controller
59
XINTREQU
O
Interrupt request signal output to the main system controller
60 to 72
SA0 to SA12
O
Address signal output to the SD-RAM
73, 74
BA0, BA1
O
Bank selection address signal output to the SD-RAM
75 to 90
SD0 to SD15
I/O
Two-way data bus with the SD-RAM
91
XSCS
O
Chip select signal output to the SD-RAM
92
XRAS
O
Row address strobe signal output to the SD-RAM
93
XCAS
O
Column address strobe signal output to the SD-RAM
94
XSWE
O
Write enable signal output to the SD-RAM
95
LDQM
O
I/O mask signal output to the SD-RAM (lower byte)
96
UDQM
O
I/O mask signal output to the SD-RAM (upper byte)
97
SDCLK
O
Clock signal output to the SD-RAM
98
SDCKE
O
Clock enable signal output to the SD-RAM
99
UA0
O
Address signal output to the USB controller and liquid crystal display unit
100 to 106
UA1 to UA7
O
Address signal output to the USB controller
107 to 114
UD0 to UD7
I/O
Two-way data bus with the USB controller and liquid crystal display unit
115
XUCS0
O
Chip select signal output to the USB controller
116
XUCS1
O
Chip select signal output to the liquid crystal display unit
117
XURD
O
Read signal output to the USB controller and liquid crystal display unit
118
XUWR
O
Write signal output to the USB controller and liquid crystal display unit
119
XUWAIT
I
Wait signal output to the USB controller
120
XUINTREQ
I
Interrupt request signal output to the USB controller
121 to 123
HA0 to HA2
I
Address signal input from the USB controller
124 to 139
HD0 to HD15
I/O
Two-way data bus with the USB controller and hard disk drive unit
140, 141 XHCS0, XHCS1
O
Chip select signal output to the hard disk drive unit
142
XHIOR
O
Read signal output to the hard disk drive unit
143
XHIOW
O
Write signal output to the hard disk drive unit
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