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20
STR-KSL50
Pin No.
53
54
55
56
57
58
59
60
61
62
63
64 to 66
67
68
69
70
71
72 to 75
76
77 to 80
81
82 to 85
86
87
88
89
90
91
92 to 97
98,99
100
101
102 to 105
106
107,108
109,110
111
112
113
114
115
116
117 to 119
120
Pin Name
PAGE0
BOOT
BTACT
BST
MOD1
MOD0
EXLOCK
VDDI
VSS
A17
A16
A15 to A13
GP10
GP9
GP8
VDDI
VSS
D15/GP7 to D12/GP4
VDDE
D11/GP3 to D8/GP0
VSS
A9 to A10
TDO
TMS
XTRST
TCK
TDI
VSS
A8 to A3
D7,D6
VDDI
VSS
D5 to D2
VDDE
D1,D0
A2,A1
VSS
A0
PM
SD13
SD14
SYNC
VSS
VDDI
I/O
O
I
O
I
I
I
I
—
—
O
O
O
O
O
I
—
—
I/O
—
I/O
—
O
O
I
I
I
I
—
O
I/O
—
—
I/O
—
I/O
O
—
O
I
I
I
I
—
—
Description
External memory page switch signal output Not used (open)
Not used (connected to the ground)
Boot mode status display signal Not used (open)
Boot strap signal input from the system control (IC1601)
Setting for 256fs (pllx9) (pull up)
Setting for single chip mode (pull down)
Lock signal input terminal
Power supply terminal (+2.5V)
Ground terminal
External memory address Not used (open)
External memory address Not used (open)
Address signal output to the SRAM (IC1202)
LRCK0 signal output
GP9 (DECODE) signal output to the system control (IC1601)
GP8 (AUDIO) signal input from the DIR (IC1101)
Power supply terminal (+2.5V)
Ground terminal
Data input/output from/to the SRAM (IC1202)
Power supply terminal (+3.3V)
Data input/output from/to the SRAM (IC1202)
Ground terminal
Address signal output to the SRAM (IC1202)
Simple emulation data output Not used (open)
Simple emulation data entry beginning and the end terminal Not used (open)
Asynchronous simple BREAK input terminal of emulation Not used (open)
Simple emulation clock input Not used (open)
Simple emulation data entry Not used (open)
Ground terminal
Address signal output to the SRAM (IC1202)
Data input/output from/to the SRAM (IC1202)
Power supply terminal (+2.5V)
Ground terminal
Data input/output from/to the SRAM (IC1202)
Power supply terminal (+3.3V)
Data input/output from/to the SRAM (IC1202)
Address signal output to the SRAM (IC1202)
Ground terminal
Address signal output to the SRAM (IC1202)
PLL initialization signal input from the system control (IC1601)
Data entry terminal Not used (open)
Data entry terminal Not used (open)
Synchronization / asynchronous selection terminal (L:Sync. H:Async.) (fixed at “H”)
Ground terminal
Power supply terminal (+2.5V)
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