Read Sony FST-GTK17IP / FST-GTK37IP / RDH-GTK17IP / RDH-GTK37IP Service Manual online
FST-GTK17iP/GTK37iP/RDH-GTK17iP/GTK37iP
59
IC603 CXD9843AR (MAIN BOARD (5/5))
IC322 TAS3108DCPR (MAIN BOARD (2/5))
12
11
10
9
8
7
6
5
4
3
VSUBC
XVSS
OUTR2
VSSR
OUTR1
VDDR
VSSL
VSSR
OUTL2
OUTL1
VSSL
VDDL
2
1
PWM
CLOCK
GENERATOR
(SECONDARY)
CLOCK
GENERATOR
(PRIMARY)
31
29
25 OVFFLAGL
26 SFLAG
27 INIT
30
S
g P
GAIN
CONTROL
INIT/
MUTE
SAMPLING
RATE
CONVERTER
FILTER &
LOW CUT
FILTER
LINER
INTERPOLATOR
'6
48
XFSOIN
47
XVDD
HPVDDL
46
45
HPOUTL1
HPVSSL
44
43
HPOUTL2
HPVDDR
42
41
HPOUTR1
HPVSSR
40
HPOUTR2
39
37
FSOCKO
38
FSOI
13
XOVSS
14
XFSOOUT
15
XOVDD
16
DVDD
17
DVSS
18
NSPMUTE
19
SOFTMUTE
20
PGMUTE
SERIAL
CONTROLLER
21
SCDT
22
SCSHIFT
23
SCLA
TCH
24
OVFFLAGR
28 MCKSEL
32 BFVDD
33 BFVSS
34 TEST
35 DVDD
36 XFSIIN
LRCK
BCK
DATA
MCLK
PLL and Clock Management
Input
SAP
Microprocessor
and
I
2
C Bus Controller
Oversample Clock
Master
SCL
N = 0 (Default)
Audio DSP Core
Output
SAP
M = 8 (Default)
8-Bit
WARP
8051 Microprocessor
M
U
X
M
U
X
M
U
X
M
U
X
M
U
X
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
OSC
÷2
÷2
÷2
÷2
÷ Z = 2DEFAULT
÷ X = 1DEFAULT
÷ Y = 64DEFAULT
M
U
X
x 11
PLL
I
2
C
Master/Slave
Controller
÷10
1/(M+1)
1/2
N
M
U
X
÷ 4
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