Read Sharp LC-46XD1E (serv.man7) Service Manual online
LC-46/52XD1E-RU
7 – 19
B23
TSIN2LERROR
I/O
Transport stream packet error (5 V tolerant)
D19
TSIN2LPACKETCLK
I/O
Transport stream packet strobe (5 V tolerant)
TS2STRT
B18,C18,D18,C19,C20,D20,
C21,D21
C21,D21
TSIN2LDATA[7:0]
I/O
Transport stream data (5 V tolerant)
TS2D[7:0]
P23
TSIN1BYTECLK
I
Transport stream bit/byte clock (5 V tolerant)
FECLK
M24
TSIN1BYTECLKVALI
D
D
I
Transport stream bit/byte clock valid edge (5 V tolerant)
FEVALID
M26
TSIN1ERROR
I
Transport stream packet error (5 V tolerant)
FEERROR
N26
TSIN1PACKETCLK
I
Transport stream packet strobe (5 V tolerant)
FESTROUT
K26,J25,H24,J24,L26,L25,
L24,M23
L24,M23
TSIN1DATA[7:0]
I
Transport stream data in (5 V tolerant)
FED[7:0]
L3
notEMIRAS or
notCI_IORD1
notCI_IORD1
O
Row address strobe for SDRAM
EMIRAS
K1
not_EMICAS or
not_CI_IOW1
not_CI_IOW1
O
Column address strobe for SDRAM
EMICAS
J1
notEMICSA
O
Peripheral chip select A
EMICSO
K3
notEMICSB
O
Peripheral chip select B
K2
notEMICSC
O
Peripheral chip select C
N4
notEMICSD
O
Peripheral chip select D
EMICS3
J2
notEMICSE
O
Peripheral chip select E
L2
notEMICSF
O
Peripheral chip select F
EMICS5
L1, N3
notEMIBE[1:0]
O
External device data bus byte enable. 1 bit per byte of the data
bus.
bus.
EMIBE1,
EMIRAS
EMIRAS
N1
notEMIOE or
not_CI_OE
not_CI_OE
O
External device output enable.
EMIOE
N2
notEMILBA or
notCI_Wea
notCI_Wea
O
Flash device load burst address.
EMILBA
P4
EMIWAITnot-
TREADY
TREADY
I
External memory device target ready indicator (5 V tolerant)
CPUWAIT
P2
EMIRDnotWR
O
External read/write access indicator. Common to all devices.
EMIRW
H3,H2,G2,H4,G4,E2,E1,E3,
H1,D1,D2,C2,G3,C1,B1,A1
H1,D1,D2,C2,G3,C1,B1,A1
EMIDATA[15:0]
I/O
External common data bus.
EMID[15-0]
D5,C5,D6,B3,A2,B2,A3,B4,
A4,C6,B5,A5,D7,C7,B6,A6,
B7,A7,D9,C9,B9,A9,B10,
C11
A4,C6,B5,A5,D7,C7,B6,A6,
B7,A7,D9,C9,B9,A9,B10,
C11
EMIADDR[25:2]
O
External common address bus
EMIA[23-2]
(D5,C5=NC)
(D5,C5=NC)
J3
notEMIREQGNT
O
Bus request/grant indicator
NC
K4
notEMIACKREQ
I
Bus grant/request indicator (5 V tolerant)
L4
EMIBOOTMODE0
I
External power-up port size indicator (5 V tolerant)
G1
EMISDRAMCLK
O
SDRAM clock
EMICLK
J4
EMIFLASHCLK
O
Peripheral clock
NC
W1,U4,U2,U1,R2,R1,T2,T1
PIO0[7:0]
I/O
Parallel input/output pin or alternative function (5 V tolerant)
(U1:MUTE,R2:VIDEOOFF,R1:MDMRESET,T2:FERE-
SET,T1:CIRESET)
(U1:MUTE,R2:VIDEOOFF,R1:MDMRESET,T2:FERE-
SET,T1:CIRESET)
AB4,Y2,AA1,Y1,W3,U3,W2,
W4
W4
PIO1[7:0]
I/O
(W2:TVRX,W4:TVTX)
AF3,AD5,AE3,AE5,AF2,Y3,
AA3,AF1
AA3,AF1
PIO2[7:0]
I/O
(AF3:ASPECT,AD5:IRQ,AA3:GPIO1,AF1:GPIO0)
AE18,AE4,AC16,AC12,AE6,
AC11,AC5,AE12
AC11,AC5,AE12
PIO3[7:0]
I/O
(AE6:TVSCL,AC11:TVSDA,AC5:I2CSCL,AE12:I2CSDA)
AE20,AD20,AF20,AE19,
AC17,AD18,AD17,AF19
AC17,AD18,AD17,AF19
PIO4[7:0]
I/O
(AE20:27MHzPWM,)
AC22,AF22,AD21,AC21,
AE21,AC18,AC20,AF21
AE21,AC18,AC20,AF21
PIO5[7:0]
I/O
(AD21:RXD,AC21:TXD,AF21:IR)
AF17
SCLK
O
Serial clock (5 V tolerant)
NC
AE17
PCMDATA1
O
PCM data out (5 V tolerant)
NC
AE16
PCMCLK
I/O
External PCM clock input or internal PCM clock output (5 V toler-
ant)
ant)
NC
AF18
LRCLK
O
Left/right clock (5 V tolerant)
TL4027
AD16
SPDIF
O
Digital audio output (5 V tolerant)
SPDIF
AD26,AB25,AB24,AC25,
AE26,AB23,AE25,AF26,
AD25,AF25,AE24,AF24,
AF23,AE23
AE26,AB23,AE25,AF26,
AD25,AF25,AE24,AF24,
AF23,AE23
SMIADDR[13:0]
O
SDRAM address bus
SMIA[13-0]
U26,U25,R23,V26,V25,T23,
V24,V23,W26,W25,Y25,
Y26,Y23,AB26,Y24,AC26
V24,V23,W26,W25,Y25,
Y26,Y23,AB26,Y24,AC26
SMIDATA[15:0]
I/O
SDRAM data bus
SMID[15-0]
T24
notSMICS0
O
SDRAM chip select for 1st SDRAM
SMICS
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