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LC-26GA5E
LC-32GA5E
LC-32GA5E
LC-37GA5E
Table 2-2
provides detailed Display/Even Port pin descriptions.
Table 2-1 Signal Descriptions for the Analog Interface Pins
Name
Pin
Type
Function
RAIN
37
AI
Red/Green/Blue Analog Inputs. These pins receive the Red, Green and
Blue, or YPbPr/YCbCr/YUV analog signals from the analog video source.
For proper operation of the clamp feature, these inputs must be
AC-coupled.
Blue, or YPbPr/YCbCr/YUV analog signals from the analog video source.
For proper operation of the clamp feature, these inputs must be
AC-coupled.
GAIN
43
AI
BAIN
50
AI
SOGIN
44
AI
Analog Sync-On-Green or Sync-On-Luma input. Allows recovery of the
HSYNC signal when this pin is AC-coupling to the Green (Red or Blue)
analog signal source. If not used, this pin should be left unconnected.
HSYNC signal when this pin is AC-coupling to the Green (Red or Blue)
analog signal source. If not used, this pin should be left unconnected.
FILT
23
AI
External PLL Loop Filter. When using the on-chip PLL, this pin must be
connected to an external filter network.
connected to an external filter network.
HSYNC
65
DIS
Horizontal Synchronization Input. This digital input signal controls the
horizontal scan frequency by synchronizing the start of the horizontal
scan. The logic polarity of this signal is controlled by the HSPOL bit.
horizontal scan frequency by synchronizing the start of the horizontal
scan. The logic polarity of this signal is controlled by the HSPOL bit.
VSYNC
64
DIS
Vertical Synchronization Input. This digital signal controls the vertical scan
frequency.
frequency.
Table 2-2 Display/Even Port Pin Descriptions
Name
Pin(s)
Type
Function
DCLK
106
OSR
DPort Pixel Clock. Output clock for the display port pixel data. DCLK is
enabled by the DCLKEN bit and can be inverted by the DCPOL bit. DCLK
can be set to run at ½ pixel rate, for dual pixel output mode, by setting the
DCK2EN bit. The internal DCLK clock domain can be disabled by the
DCLKOFF bit to reduce power consumption.
enabled by the DCLKEN bit and can be inverted by the DCPOL bit. DCLK
can be set to run at ½ pixel rate, for dual pixel output mode, by setting the
DCK2EN bit. The internal DCLK clock domain can be disabled by the
DCLKOFF bit to reduce power consumption.
DCLKNEG
107
OSR
DPort Pixel Clock.
DVS
101
OS
DPort Vertical Sync. DVS can be either active-high or active-low depending
on the VSPOL bit. Width and timing is controlled by the VPLSE and VDLY
registers.
on the VSPOL bit. Width and timing is controlled by the VPLSE and VDLY
registers.
DHS
102
OS
DPort Vertical Sync. DHS can be either active-high or active-low depending
on the HSPOL bit. Sync width can be controlled by the HPLSE register.
on the HSPOL bit. Sync width can be controlled by the HPLSE register.
DEN
103
OS
DPort Pixel Enable. This signal is active whenever valid data is present.
The polarity is specified by the DENPOL bit.
The polarity is specified by the DENPOL bit.
3.3. Description of Pins IC2201
CONFIDENTIAL
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