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LC-37AD5E
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2.7. ICIC1710 (RH-IXB823WJZZQ)
2.7.1 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
Sheet Name
1
EXP [7]
O
Outport [7] (I2C SEL signal)
DTI2CSEL
2
EXP [6]
O
Outport [6] (Digital circuit reset signal)
DTM_RESET
3
EXP [5]
O
Outport [5] (Digital circuit power control signal)
DTV_ON
4
GND*
–
Ground
N.C.
5
EXP [3]
O
Outport [3] (Inverter ON control signal)
BL_ON
6
GND*
–
Ground
N.C.
7
OFLOUT
O
OFL signal output
OFLOUT
8
OSCOUT
O
OSC signal output
OSCOUT
9
VCCIO1
–
VCC (3.3V)
FPGA_VCC
10
GNDIO
–
Ground
Ground.
11
GNDINT
–
ground.
Ground.
12
PCLK
I
Reference clock input
PCLK
13
VCCINT
–
VCC (3.3V)
FPGA_VCC
14
GCLR
I
RESET terminal. L: RESET, H: Normal
RESET_N
15
GND*
–
N.C.
N.C.
16
GND*
–
N.C.
N.C.
17
GND*
–
N.C.
N.C.
18
GND*
–
N.C.
N.C.
19
GND*
–
N.C.
N.C.
20
GND*
–
N.C.
N.C.
21
GND*
–
N.C.
N.C.
22
#TMS
I
Pin for JTAG write (Test Mode Select)
FPGA_TMS
23
#TDI
I
Pin for JTAG write (Test Data Input)
FPGA_TDI
24
#TCK
I
Pin for JTAG write (Test Clock)
FPGA_TCK
25
#TDO
O
Pin for JTAG write (Test Data Input)
FPGA_TDO
26
VSYNC
I
V sync input (not used)
V_SYNC
27
HSYNC
I
H sync input (not used)
H_SYNC
28
GND*
–
N.C.
N.C.
29
GND*
–
N.C
N.C.
30
DMY_IN
I
Dummy pin for RESET line wiring (no effect on operation)
RESET_N
31
VCCIO1
–
VCC (3.3V)
FPGA_VCC
32
GNDIO
–
Ground.
Ground.
33
GND*
–
N.C.
N.C.
34
GND*
–
N.C.
N.C.
35
SCK
I
Microprocessor control bus clock
SCK
36
GND*
–
N.C.
N.C.
37
GND*
–
N.C.
N.C.
38
GND*
–
N.C.
N.C.
39
GND*
–
N.C.
N.C.
40
GND*
–
N.C.
N.C.
41
SEN
I
Microprocessor control bus enable
SDE
42
SDA
I
Microprocessor control bus data
SDA
43
GND*
–
N.C.
N.C.
44
GND*
–
N.C.
N.C.
45
VCCIO1
–
VCC (3.3V)
FPGA_VCC
46
GNDIO
–
Ground.
Ground.
47
GND*
–
N.C.
N.C.
48
GND*
–
N.C.
N.C
49
GND*
–
N.C.
N.C.
50
GND*
–
N.C.
N.C.
51
GND*
–
N.C.
N.C.
52
GND*
–
N.C.
N.C.
53
GND*
–
N.C.
N.C.
54
GND*
–
N.C.
N.C.
55
GND*
–
N.C.
N.C.
56
GND*
–
N.C.
N.C.
57
GND*
–
N.C.
N.C.
58
GND*
–
N.C.
N.C.
59
VCCIO2
–
VCC (3.3V)
FPGA_VCC
60
GNDIO
–
Ground.
Ground.
61
GND*
–
Ground.
N.C.
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