Read Sharp 76FW-53H (serv.man13) Service Manual online
Colour Television – DA100/DW100 Chassis
Sharp Electronics (UK) Ltd
Technical Support
September 99
Page 11
VIDEO AND SYNC PROCESSOR
This IC is a member of the ‘Micronas’ VDP 31xxB IC family, which are high-quality video processors
Allowing the economic integration of features in all classes of TV sets. The VDP 31xxB family is
based on functional blocks contained in the two previous chips form Micronas:
Allowing the economic integration of features in all classes of TV sets. The VDP 31xxB family is
based on functional blocks contained in the two previous chips form Micronas:
VPC 3200A Video Processor
DDP 3300A Display and Deflection Processor
DDP 3300A Display and Deflection Processor
VDP 31xxB contains the entire video, display, and deflection processing for 4:3 and 16:9 CTV’s
operating at either 50 or 60Hz featuring:
operating at either 50 or 60Hz featuring:
2H adaptive Comb-filter
Scan Velocity Modulator.
1H Comb-filter
Colour Transient Improvement.
RGB Insertion
Tube Control
Programmable RGB Matrix
4 composite inputs (one for S-VHS)
Composite video & sync output
Horizontal scaling (0.25 to 4)
Panorama vision
Black level expander
Dynamic peaking
Soft-limiter (gamma correction)
Picture frame generator
High-performance H/V deflection
Separate ADC for tube measurements
EHT compensation
One 20.25 MHz crystal (for all systems), few external components
Embedded RISC controller (80 MIPS)
I
Scan Velocity Modulator.
1H Comb-filter
Colour Transient Improvement.
RGB Insertion
Tube Control
Programmable RGB Matrix
4 composite inputs (one for S-VHS)
Composite video & sync output
Horizontal scaling (0.25 to 4)
Panorama vision
Black level expander
Dynamic peaking
Soft-limiter (gamma correction)
Picture frame generator
High-performance H/V deflection
Separate ADC for tube measurements
EHT compensation
One 20.25 MHz crystal (for all systems), few external components
Embedded RISC controller (80 MIPS)
I
2
C-Bus Interface
Single 5 V power supply
D
ESCRIPTION
A
NALOGUE FRONT
-
END
This block provides the analogue interfaces to all video inputs and mainly carries out analogue-to
digital conversion for the following digital video processing.
digital conversion for the following digital video processing.
Most of the functional blocks in the front-end are digitally controlled (clamping, AGC, and clock-DCO).
The control loops are closed by the Fast Processor (‘FP’) embedded in the decoder.
The control loops are closed by the Fast Processor (‘FP’) embedded in the decoder.
I
NPUT
S
ELECTOR
Up to five analogue inputs can be connected. Four inputs are for input of composite video or S-VHS
luma signal. These inputs are clamped to the sync back porch and are amplified by a variable gain
amplifier. One input is for connection of S-VHS chrominance signal. This input is internally biased and
has a fixed gain amplifier.
luma signal. These inputs are clamped to the sync back porch and are amplified by a variable gain
amplifier. One input is for connection of S-VHS chrominance signal. This input is internally biased and
has a fixed gain amplifier.
C
LAMPING
The composite video input signals are AC coupled to the IC. The clamping voltage is stored on the
coupling capacitors and is generated by digitally controlled current sources. The clamping level is the
back porch of the video signal. S-VHS chroma is also AC coupled. The input pin is internally biased to
the centre of the ADC input range.
coupling capacitors and is generated by digitally controlled current sources. The clamping level is the
back porch of the video signal. S-VHS chroma is also AC coupled. The input pin is internally biased to
the centre of the ADC input range.
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