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XG-NV1U
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5. YUV-bus (digital outputs)
The 16-bit YUV-bus transfers digital data from the output interfaces to a feature box, or a field memory.
The output are controlled by an output enable chain (FEIN on pin 63).
The YUV data rate equals LLC2. Timing is acheived by marking each second positive rising edge of the clock LLC
in conjunction with CREF (clock reference).
in conjunction with CREF (clock reference).
The output signals Y7 to Yo are the bits of the digital luminance signal. The output signals UV7 to UV0 are the bits
of multiplexed colour difference signals (B-Y) and (R-Y). The frame in the format tables is the time, required to
transfer a full set of samples. In the event of 4:2:2 format two luminance samples are transmitted in comparison to
one U and one V sample within the frame.
The time frames are controlled by the HREF signal.
of multiplexed colour difference signals (B-Y) and (R-Y). The frame in the format tables is the time, required to
transfer a full set of samples. In the event of 4:2:2 format two luminance samples are transmitted in comparison to
one U and one V sample within the frame.
The time frames are controlled by the HREF signal.
Fast enable is achieved by setting input FEIN to LOW. The signal is used to control fast switching on the digital
YUV-bus. HIGH on this pin forces the Y and UV outputs to a high-impedance state.
YUV-bus. HIGH on this pin forces the Y and UV outputs to a high-impedance state.
6. Synchronization (see Figure 8-5. )
The pre-filtered luminance signal is fed to the synchronization stage. It's bandwidth is reduced to 1 MHz in a low-
pass filter.
pass filter.
The synchronization pulses are sliced and fed to the phase detectors where they are compared with the sub-
divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations.
Adjustable output signals HCL and HSY are generated in accordance with analog front end requirements. The
output signals HS, VS, and PLIN are locked to the timing reference, guaranteed between the input signal and the
HREF signal, as further improvements to the circuit may change the total processing delay. It is therefore not
recommended to use them for applications which require absolute timing accuracy to the input signals. The loop
filter signal drives an oscillator to generate the line frequency control signal LFCO.
divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations.
Adjustable output signals HCL and HSY are generated in accordance with analog front end requirements. The
output signals HS, VS, and PLIN are locked to the timing reference, guaranteed between the input signal and the
HREF signal, as further improvements to the circuit may change the total processing delay. It is therefore not
recommended to use them for applications which require absolute timing accuracy to the input signals. The loop
filter signal drives an oscillator to generate the line frequency control signal LFCO.
7. Clock generation circuit
The internal CGC generates all clock signals required for the one chip front-end. The output signal LFCO is a
digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency (7.38 MHz
= 472 x fn in 50 Hz systems and 6.14 MHz = 360 x fn in 60Hz systems). Internally the LFCO signal is multiplied by
a factor of 2 or 4 in the PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the
LLC and LLC2 output clock signals. The rectangular output clocks have a 50% duty factor.
digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency (7.38 MHz
= 472 x fn in 50 Hz systems and 6.14 MHz = 360 x fn in 60Hz systems). Internally the LFCO signal is multiplied by
a factor of 2 or 4 in the PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the
LLC and LLC2 output clock signals. The rectangular output clocks have a 50% duty factor.
8. Power-on reset
Power-on reset is activated at power-on (using only internal CGC), when the supply voltage decreases below 3.5 V.
The indicator RESET is LOW for a time. THe RESET signal can be applied to reset other circuits of the digital TV
system.
The indicator RESET is LOW for a time. THe RESET signal can be applied to reset other circuits of the digital TV
system.
9. RTCO output
The real time control and status output signal contains serial information about actual system clock, subcarrier
frequency and PAL/SECAM sequence. The signal can be used for various applications in external circuits, forexample,
in a digital encoder to achieve clean encoding.
frequency and PAL/SECAM sequence. The signal can be used for various applications in external circuits, forexample,
in a digital encoder to achieve clean encoding.
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