Read Sharp AR-F151 (serv.man13) Service Manual online
(4) CPU interface
Terminal
name
Pin
No.
I/O
Function
CS
1
I
Chip select for the CPU to access
the LC8213 (low sctive).
the LC8213 (low sctive).
RD
2
I
Read.Set to “L” when the CPU is
the read out the LC8213 register.
the read out the LC8213 register.
WR
3
I
Write.Set to “L” when the CPU is
to the LC8213 register.
to the LC8213 register.
A2
4
I
Address input for when the CPU
accesses LC8213.
accesses LC8213.
A1
5
A0
6
D7
9
I/O
3 state
Bidirectional 8-bit data bus
D6
10
D5
11
D4
12
D3
14
D2
15
D1
16
D0
17
IREQ
20
O
Interrupt request signal for the
CPU. By reading out the INTR
(interrupt request register) the CPU
can find the cause of the
interruption.IREQ is set to “L” when
the CPU reads INTR.
CPU. By reading out the INTR
(interrupt request register) the CPU
can find the cause of the
interruption.IREQ is set to “L” when
the CPU reads INTR.
DREQ
21
O
DMA request signal for the external
DMA controller. This will be set to
“H” in the following cases.
DMA controller. This will be set to
“H” in the following cases.
• Data exists in the EFIFO during
the coding processes.
• An empty space exists in the
DFIFO during decoding processes.
• The DBUF can read/write during
data transfer between the image
memory bus and CPU bus.
memory bus and CPU bus.
DACK
22
I
DMA acknowledge signal from the
external DMA comtroller.If DACK is
set to “L” during coding or
decoding, EFIFO and DFIFO will
be accessed. DBUF will be
accessed if DACK is set to “L”
during data transfer between the
image memory bus and CPU bus.
external DMA comtroller.If DACK is
set to “L” during coding or
decoding, EFIFO and DFIFO will
be accessed. DBUF will be
accessed if DACK is set to “L”
during data transfer between the
image memory bus and CPU bus.
(5) Image memory interface
Terminal
name
Pin
No.
I/O
Function
MA23
54
O
3 state
Not used.
MA22
55
MA21
56
MA20
57
MA19
56
MA18
59
MA17
60
MA16
61
MA/MD15
62
I/O
3 state
Not used.
MA/MD14
64
Low-order 16-bit address and 16-
bit data bus for the image memory.
bit data bus for the image memory.
MA/MD13
65
MA/MD12
66
MA/MD11
67
MA/MD10
68
MA/MD9
69
MA/MD8
70
Terminal
name
Pin
No.
I/O
Function
MA/MD7
71
MA/MD6
74
MA/MD5
75
MA/MD4
76
MA/MD3
77
MA/MD2
78
MA/MD1
79
MA/MD0
80
AEN
41
O
This is set to “L” when the
LC8213 is the bus master to the
image memory.
If AEN = “H”, MA/MD, MRD,
MWR, IORD, IOWR, UDE and
LDE will be a HiZ output.
LC8213 is the bus master to the
image memory.
If AEN = “H”, MA/MD, MRD,
MWR, IORD, IOWR, UDE and
LDE will be a HiZ output.
AST
42
O
This signal indicates that an
address is being output to
MA/MD15
address is being output to
MA/MD15
∼ MA/MD0.
MDEN
43
O
This signal indicates that the
LC8213 is using MA/MD15
LC8213 is using MA/MD15
∼
MD0 as data buses.
USE
49
I/O
3 state
Not used.
LDE
48
I/O
3 state
This signal indicates that the low-
order bits of the data bus are
being used.
order bits of the data bus are
being used.
MRD
44
O
3 state
This is set to “L” when data is
being read out of the image
memory.
being read out of the image
memory.
MWR
45
O
3 state
This is set to “L” when data is
being written into the image
memory.
being written into the image
memory.
IORD
46
O
3 state
Not used.
IOWR
47
O
3 state
Not used.
BREQ
37
O
This signal is used for the LC8213
to request usage rights from the
image memory bus.
to request usage rights from the
image memory bus.
BACK
38
I
Input signal allowing the LC8213
to use the image memory bus.
to use the image memory bus.
IDREQ
39
I
Not used.
IDACK
40
O
Not used.
READY
50
I
This signal is used to delay the
read/write signal when using low
speed image memory or an I/O
device.
read/write signal when using low
speed image memory or an I/O
device.
DTC
51
O
Not used.
(6) Others
Terminal
name
Pin No.
I/O
Function
CKL
28
I
External clock (Max.20NHz)
RESET
27
I
Reset
TEST0
35
I
For testing.This is normally fixed
to “L”.
to “L”.
TEST1
34
TEST2
33
TEST3
32
TEST4
30
V
DD
7, 31,
73
73
power supply (+ 5V)
V
SS
13, 29,
52, 63,
72
52, 63,
72
GND
AR-F151
11 – 17
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