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Interface timing table
Item
Symbol
Rating
Unit
Min.
Typ.
Max.
Frame frequency
T
FRM
(Note 1)
8.0
16.9
ms
Clock frequency
T
CP2
152
ns
HIGH level clock width
t
CWH
65
ns
LOW level clock width
t
CWL
65
ns
HIGH level latch clock width
t
LWH
70
ns
Data setup time
t
SU
50
ns
Data hold time
t
H
40
ns
Scan start signal setup time
t
SSU
100
ns
Scan start signal hold time
t
SH
100
ns
Clock allowance time from
CP2
CP2
↓
to CP1
↑
t
S21
0
ns
Clock allowance time from
CP1
CP1
↓
to CP2
↑
t
S12
0
ns
Clock rising/falling time
tr, tf
(Note 2)
trf
ns
(Note 1) The frame frequency (min. 8ms, max q25Hz) is specified
only for the operations.
(Note2)
When CP2 is driven at high speeds, trf is determined by t
CT
in the following formula:
When t
When t
CT
= (T
cp2
– t
CWH
– t
CWL
)/2
u
50, trf = 50
When t
CT
= (T
cp2
– t
CWH
– t
CWL
)/2 < 50, trf = tCT
5. Unit drive procedure
1) Circuit composition
See Fig. 9 on the next page.
2) Screen composition
The display (640
×
480 dot) of this unit is divided into two sections
(the upper half and the lower half) to reduce duty number and provide
high contrast. Each half (640
high contrast. Each half (640
×
240 dot) is driven by 1/240 duty.
3) Input data and control signals
The LCD driver is an 80 bit LSI which is composed of the soft register,
and latch circuit, and the LCD drive circuit.
and latch circuit, and the LCD drive circuit.
Input data are sequentially transmitted from the upper left of each
screen by one line (640 dot) together with clock pulse CP2 through he
shift register as the 4 bit parallel data.
When one line data (= 640 dot data) are inputted, they are latched as
parallel data for 640 signal electrodes at falling edge of latch signal
CP1. The drive signals corresponding to 640 signal electrodes of the
LCD panel are sent to the signal electrodes.
screen by one line (640 dot) together with clock pulse CP2 through he
shift register as the 4 bit parallel data.
When one line data (= 640 dot data) are inputted, they are latched as
parallel data for 640 signal electrodes at falling edge of latch signal
CP1. The drive signals corresponding to 640 signal electrodes of the
LCD panel are sent to the signal electrodes.
At that time, the scan start signal S inputted to the scan signal drive
circuit is transmitted to the first line to display the signal data in the
first line of each screen in combination with the voltage applied to the
signal electrode.
While the first line data is displayed, the second line data is inputted.
When 640 dot data are transmitted, they are latched at falling edge of
CP1, changing the display to the second line.
circuit is transmitted to the first line to display the signal data in the
first line of each screen in combination with the voltage applied to the
signal electrode.
While the first line data is displayed, the second line data is inputted.
When 640 dot data are transmitted, they are latched at falling edge of
CP1, changing the display to the second line.
As stated above, data inputs are repeated from the top to the bottom
until the 240th line to complete one screen (1 frame). Then the first
line data is inputted again. The scan start signal drives the horizontal
electrodes.
until the 240th line to complete one screen (1 frame). Then the first
line data is inputted again. The scan start signal drives the horizontal
electrodes.
If a DC voltage is applied to the LCD panel, the LCD in the panel is
deteriorated by chemical change. Therefore the drive voltage must be
AC in order to prevent against generation of a DC voltage. This is
performed by the drive waveform AC signal generation circuit.
deteriorated by chemical change. Therefore the drive voltage must be
AC in order to prevent against generation of a DC voltage. This is
performed by the drive waveform AC signal generation circuit.
Fig. 9 Circuit composition block diagram
As the feature of the CMOS driver LSI, the power consumption of the
unit increases as CP2 clock frequency increases. Therefore, the
driver LSI is provided with four shift registers which reduce CP2 clock
data transmitting speed and transmit the 4 bit parallel data.
unit increases as CP2 clock frequency increases. Therefore, the
driver LSI is provided with four shift registers which reduce CP2 clock
data transmitting speed and transmit the 4 bit parallel data.
The LSI reduces the power consumption of the unit. In this circuit
configuration, 4 bit display data are inputted from the data input pin of
DU0
configuration, 4 bit display data are inputted from the data input pin of
DU0
∼
3 (upper half screen) and DL0
∼
3 (lower half screen). In
addition, the LCD unit is provided with the data input bus line system
which reduces the power consumption.
which reduces the power consumption.
This system allows the LSI data input to function only when proper
data are sent.
data are sent.
Data input of the signal electrodes of the upper and lower screens
and the driver LSI chip select are shown below:
and the driver LSI chip select are shown below:
The driver LSI at the left end on the screen is first selected. When 80
dot data (20CP2) are supplied, the right adjacent driver LSI is se-
lected.
This process is repeated sequentially until the data are sent to the LSI
at the right end of the screen.
dot data (20CP2) are supplied, the right adjacent driver LSI is se-
lected.
This process is repeated sequentially until the data are sent to the LSI
at the right end of the screen.
This process occurs simultaneously at the signal electrode drive LSI
in the upper and the lower screens.
As stated above, data input of the upper and the lower screens are
sent through 4 bit bus line sequentially.
in the upper and the lower screens.
As stated above, data input of the upper and the lower screens are
sent through 4 bit bus line sequentially.
Since this graphic display unit does not include a refresh RAM, the
above data and timing pulse must be inputted in a still screen also.
above data and timing pulse must be inputted in a still screen also.
Control
LSI
RAM
C
P
U
P
U
DL0~DL3
S
CP1
CP2
DISP
DU0~DU3
SEG Drivers (Upper)
SEG Drivers (Lower)
V
DD
, V
SS
, V
EE
*2 BG
*1 MG: M GENERATOR CIRCUIT
*2 BG: BIAS GENERATOR CIRCUIT
*2 BG: BIAS GENERATOR CIRCUIT
CO
M
D
ri
v
e
rs
640 X 480 LCD panel
*1 MG
M
Inverter
CCFT
B/L
– 82 –
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