Read Sharp UP-600 / UP-700 (serv.man20) Service Manual online
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CHAPTER 12. CIRCUIT DIAGRAM
1. CPU
VCC
LD0
LD1
LD2
LD3
LD4
LD5
LD6
1
8
2
7
3
6
4
5
BR1
10k
*4
1
8
2
7
3
6
4
5
BR2
10k
*4
LD[0
:7]
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
VCC
HD[0:7
]
2
1
C41
470
pF
P
LLV
CC
2
1
C43
0.1
u
F
P
LLV
SS
1
8
2
7
3
6
4
5
BR3
33*
4
1
8
2
7
3
6
4
5
BR4
33*
4
2
1
(C3
)
18p
F
2
1
(C4
)
18p
F
VCC
R70
3k
R71
200
R4
10k
R3
10k
R2
10k
2
1
C42
0.1
u
F
R75
10k
X1
5M
Hz
CST
C
R
R7
680
R76
10k
(R5
)
10k
(R6
)
10k
SH
70
14
/LRES
H
D
0
H
D
1
/RT
S
1
/DT
R
1
/DCD1
/CI1
/DSR1
VCC
/CT
S
1
R139
10k
R138
10k
P
LLV
SS
R1
10k
PE
0/
T
I0C
0
A
/D
R
E
Q
0
85
PE
1/T
IO
C
0
B
/DRA
K0
86
D12
56
P E 1 4 / D A C K 0 / ~ A H
1
R E S
8
4
P E 1
5 /
D A C K 1
2
V S S
3
A 0
4
A 1
5
A 2
6
A 3
7
A 4
8
A 5
9
A 6
1
0
A 7
1
1
A 8
1
2
A 9
1
3
A 1 0
1
4
A 1 1
1
5
A 1 2
1
6
A 1 3
1
7
A 1 4
1
8
A 1 5
1
9
A 1 6
2
0
V C C
2
1
A 1 7
2
2
V S S
2
3
P B 2 / ~ I R Q 0 / ~ R A S
2
4
P B 3 / ~ I R Q 1 / ~ C A S L
2
5
P B 4 / ~ I R Q 2 / ~ C A S H
2
6
V S S
2
7
P B 5 / ~ I R Q 3 / R D W R
2
8
PE
2
/T
IO
C
0C/DREQ1
87
PE
3
/T
IO
C
0D/DRAK
1
88
PE
4/T
IO
C
1
A
89
VS
S
90
PF
0
/A
N
0
91
PF
1
/A
N
1
92
PF
2
/A
N
2
93
PF
3
/A
N
3
94
PF
4
/A
N
4
95
PF
5
/A
N
5
96
AV
SS
97
PF
6
/A
N
6
98
PF
7
/A
N
7
99
AV
CC
100
VS
S
101
PE
5/T
IO
C
1
B
102
VCC
103
PE
6/T
IO
C
2
A
104
PE
7/T
IO
C
2
B
105
PE
8
106
PE
9
107
PE
10
108
VS
S
109
PE
11
110
PE
12
111
PE
13
112
P A 1
5 /
C
K
8
3
PB
6/A
1
8
29
PB
7/A
1
9
30
PB
8
/IRQ6/
A
20
/WAIT
31
P L L
V S
S
8
2
P L L
C A
P
8
1
P L L
V C C
8
0
M D 0
7
9
M D 1
7
8
V C C
7
7
N M I
7
6
M D 2
7
5
E X T
A L
7
4
M D 3
7
3
X T A
L
7
2
V S S
7
1
D 0
7
0
D 1
6
9
D 2
6
8
D 3
6
7
D 4
6
6
V C C
6
5
D 5
6
4
D 6
6
3
D 7
6
2
V S S
6
1
D 8
6
0
D 9
5
9
D 1 0
5
8
D 1 1
5
7
VS
S
55
D13
54
D14
53
D15
52
PA
0
/RX
D0
51
PA
1/T
X
D0
50
PA
2
/S
C
K0/DREQ0/
IRQ0
49
PA
3
/RX
D1
48
PA
4/T
X
D1
47
PA
5
/S
C
K1/DREQ1/
IRQ1
46
PA
6/T
C
L
KA/CS2
45
PA
7/T
C
L
KB/CS3
44
PA
8
/TCLKC/IRQ
2
43
PA
9
/TCLKD/IRQ
3
42
CS0
41
CS1
40
VS
S
39
WRL
38
VCC
37
WRH
36
WDT
O
V
F
35
RD
34
VS
S
33
PB
9
/IRQ7/
A
21
32
IC1
CPU_S
H
7
014
CPU
R73
10k
R74
10k
1
8
2
7
3
6
4
5
B
R
13
10k
*4
1
8
2
7
3
6
4
5
B
R
11
10k
*4
1
8
2
7
3
6
4
5
B
R
12
10k
*4
H
D
2
H
D
3
H
D
4
H
D
5
H
D
7
H
D
6
H
D
8
H
D
9
H
D
1
0
H
D
1
1
HD12
HD13
HD14
HD15
/M
WE
/CS1
/CS0
/CS3
VCC
RXD1
TX
D
1
/CSDP
R
AM
1
8
2
7
3
6
4
5
BR5
10k
*4
1
8
2
7
3
6
4
5
BR6
10k
*4
1
8
2
7
3
6
4
5
BR1
8
10k
*4
1
8
2
7
3
6
4
5
BR1
7
10k
*4
LD7
VCC
R132
10k
R133
10k
2
1
C5
2
1
C6
2
1
C7
2
1
C8
2
1
C9
2
1
C10
2
1
C11
2
1
C12
100
pF*
8
1
8
2
7
3
6
4
5
BR8
1
8
2
7
3
6
4
5
BR9
1
8
2
7
3
6
4
5
BR1
0
1
8
2
7
3
6
4
5
BR7
10k
*4
10k
*4
10k
*4
10k
*4
VCC
LA
[0:
17]
LA
0
LA
1
LA
2
LA
3
LA
4
LA
5
LA
6
LA
7
LA
8
LA
9
LA
10
LA
11
LA
12
LA
13
LA
0
LA
1
LA
2
LA
3
LA
4
LA
5
LA
6
LA
7
LA
8
LA
10
LA
11
LA
12
LA
13
LA
9
VCC
/INT
H
W
/INT
H
R
/INT
L
AN
LA
[0:
17]
L
A
1
3
L
A
1
4
L
A
1
5
L
A
1
6
L
A
1
7
IOCHRDY
/M
RD
R15
10k
LA
19
LA
18
R130
10k
VCC
R131
10k
LA
19
R136
10k
R8
10k
2
1
C40
100
pF
LA
18
2
1
C39
100
pF
2
1
C1
0.1
u
F
/RST
DRV
/HWACK
/HRACK
/SWRE
Q
/SRRE
Q
L
A
0
L
A
1
L
A
2
L
A
3
L
A
4
L
A
5
L
A
6
L
A
7
L
A
8
L
A
9
L
A
1
0
L
A
1
1
L
A
1
2
VCC
R121
10k
VCC
D4
LE
D
C2
10u
F
1
8
2
7
3
6
4
5
BR1
4
10k
*4
R72
10k
R141
470
WP#
/CSF
LA
SH
/CS3
/CSL
AN
PE
12
R69
10k
1
3
2
4
5
6
SW1
Q1
K
RC106S
LA
[0:
17]
VCC
/CSE
PROM
/CS0
/CSF
LA
SH
R129
10k
LA
14
LA
15
LA
16
LA
17
2
1
C21
2
1
C22
2
1
C23
2
1
C24
2
1
C25
2
1
C26
2
1
C27
2
1
C28
2
1
C29
2
1
C30
2
1
C31
2
1
C32
2
1
C33
2
1
C34
2
1
C35
2
1
C36
2
1
C37
2
1
C38
100
pF*
1
8
C21~38
LA
14
LA
15
LA
16
LA
17
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