ER-A490 (serv.man4). ERA490 Option Service Manual - Sharp ECR Service Manual (repair manual). Page 29

The MB89371A (Serial data transmitter/receiver, 2 units) is a versa-
tile-use interface LSI for communication lines, which is equipped with
two sets of equivalent units of the MB89251A (serial data transmit-
ter/receiver), the baud rate generating section, and the interruption
adjustment section. 
It is positioned between the line Modem and the computer, and used
for serial/parallel conversion of data, data send/receive operation
check, and the synchronization mode selection according to the pro-
gram assignment. 
The transmitter section converts parallel data into serial data, and
adds the parity bit, the start bit, and the stop bit to them, and transmits
them. In the synchronization mode, it transmits synchronization char-
acters during no transmission data period. In the advancement syn-
chronization mode, it allows selection of transmission clocks and
transmission baud rates. 
The receiving section converts serial data into parallel data, and
checks parities to judge that data are properly transmitted. 
In the synchronization mode, it detects synchronization characters
and makes synchronization of transmission/reception operations with
the transmitter side. In the advancement synchronization mode, it
allows selection of transmission clocks and reception baud rates. 
The baud rate generating section generates clock pulse signals which
are used in transmission and reception and delivered through the
baud rate selecting section to the SDTR section. 
It provides the loop back diagnostic function which crosses interface
lines of the Modem and loops transmission and reception signals,
facilitating the operation check. 

●

Two independent channels of SDTR.

●

Built-in baud rate generator which allows setting for each channel

●

External clock available

●

Internal clock output available. 

●

Maskable interruption generating circuit

●

Two channels are assigned to different address spaces. 

●

Baud rate DC ~ 240K baud (with external clocks)

●

Full duplex communication

●

Program assignment in synchronization mode

•

Data bit length: 5 - 8 bits

•

Character synchronization system: Internal synchronization, 
external synchronization

•

Number of synchronized characters: Single character, double
characters

•

Parity occurrence and check: parity valid/invalid 

even parity, odd parity

●

Operations in the synchronization mode  

•

Overrun error and parity error detection

•

Transmit/receive buffer state acknowledgment

•

Synchronization character detection

•

Automatic insertion of synchronization character 

●

Program assignment function in the advancement synchronization
mode

•

Data bit length: 5 ~ 8 bits

•

Stop bit length: 1, 1

1

⁄

2

, 2 bits

•

Baud rate: Transmission clock, reception clock x 1, x 1/16, x
1/64

•

Parity occurrence and check: Parity valid, invalid 

Even parity, odd parity

●

Operations in the advancement synchronization mode

•

Detection of framing error, overrun error, parity error 

•

Transmission/reception buffer state acknowledgment

•

Break characters detection

●

Error start bit detection

●

IBM Bi-sync system operation allowed.

●

Duplex buffer system in the transmission and the reception sec-
tions. 

●

Loop back diagnostic functions

●

I/O signal level TTL compatible

●

Compatible with standard microprocessor in connecting pins and
signal timing.

●

Standard 42 pin plastic DIP, 48 pin plastic QFP

●

+5V single power source

1

DB4

2

DB5

3

DB6

4

DB7

5

TRNCLK1

6

W

7

CS1

8

RSLCT0

9

R

10

RCVRDY1

11

RSLCT1

12

CS2

48

N

C

47

GN

D

46

R

C

V

D

T

1

45

D

B

3

44

D

B

2

4

3

O

PEN

42

D

B

1

41

D

B

0

40

V

C

C

39

R

C

V

C

L

K

1

38

N

C

3

7

DT

R1

36

RTS1

35

DSR1

34

RST

33

CLOCK

32

TRNDT1

31

TRNEMP1/ST1-1

30

CTS1

29

SYNC/BRK1

28

TRNRDY1

27

RCVCLK2

26

DTR2

25

RTS2

13

RC

V

D

T

2

14

NC

15

T

RNCL

K

2

16

RCV

RDY

2

17

TR

N

R

D

Y

2

18

SYN

C

/BR

K2

19

O

PEN

20

CT

S

2

21

T

R

N

E

M

P

2/

S

T

1-

2

22

TR

N

D

T2

23

DS

R2

24

NC

DB0~DB7

CS1,CS2

RSLCT0,RSLCT1

W,R

TRNRDY1
RCVRDY1

SYNC,BRK1

TRNEMP1

RST

TRNRDY2
RCVRDY2

SYNC/BRK2

TRNEMP2

CLOCK

SDTR1

TRNDT1
RTS1
DTR1

RCVDT1

CTS1
DSR1

TRNCLK1

RCVCLK1

SDTR2

TRNDT2
RTS2

DTR2

RCVDT2
CTS2
DSR2

TRNCLK2

RCVCLK2

Address

decoder

Mode setting

register 1

Baud rate

setting

register 1

Baud rate

generator

Mode setting

register 2

Baud rate

setting

register 2

Interrup-

tion

mask 1

Loop

back

control

1

Loop

back

control

2

Interrup-

tion

mask 2

Clock

control

1

Clock

control

2

VCC

GND

3 – 5