Read Sharp DV-560H (serv.man2) Service Manual online
DV-560H
12-21
Pin No. Terminal name
I/O
Operation function
Remarks
25
ED0
–
User use is prohibited (N.C.) since it is for shipping adjustment.
Open
26
ED1
–
27
ED2
–
28
ED3
–
29
ED4
–
30
ED5
–
31
ED6
–
32
ED7
–
33
TEST
I
For shipping adjustment.
Set to “L”
34
PDON
O
PLL phase error signal output. (Negative polarity)
35
PDOP
O
PLL phase error signal output. (Positive polarity)
36
RLLD
O
RLL detection result output.
37
LPFN
I
PLL loop filter amp. reverse input.
38
LPFO
O
PLL loop filter amp. output.
39
VCOF
O
VCO filter terminal.
40
SLCO
O
Built-in comparator reference voltage output terminal.
41
AVSS
–
Analog power. (0V)
42
AVR
O
Non-PLL system analog reference potential. (1.65V)
43
VRC
–
Resistance division point potential. (For analog reference
potential generation: 1.65)
44
PVR
O
PLL system analog reference potential. (1.65V)
45
AVDD
–
Analog power. (3.3V)
46
RVR2
–
2nd reference voltage. (For capacitor connection)
47
RVDD
–
Exclusive-use power terminal. (3.3V)
48
RFIN
I
RF signal input.
49
RVSS
–
Exclusive-use power terminal. (0V)
50
RVR1
–
1nd reference voltage. (For capacitor connection)
51
DVR
I
DMO reference potential. (1.65V recommended)
52
DMO
O
Disc equalizer output for DVD. (Triple value PWM + HiZ)
53
RASN
O
External RAM row address selection. (Negative logic)
54
CASN
O
External RAM row address selection. (Negative logic)
55
MOEN
O
External RAM output permission signal.
56
MWEN
O
External RAM read/write selection.
57
DVSS
–
Digital power. (0V)
For logic cell
58
DVDD3
–
Digital power. (3.3V)
For logic cell
59
MA9
O
External RAM address bus.
60
MA8
O
External RAM address bus.
61
MA7
O
External RAM address bus.
62
MA6
O
External RAM address bus.
63
MA5
O
External RAM address bus.
64
MA4
O
External RAM address bus.
65
MA3
O
External RAM address bus.
66
MA2
O
External RAM address bus.
67
MA1
O
External RAM address bus.
68
MA0
O
External RAM address bus.
69
DVSS
–
Digital power. (0V)
For I/O cell
70
DVDD5
–
Digital power. (5V)
For I/O cell
71
MD7
I/O
External RAM data bus.
TTL level
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