SM-SX100 (serv.man2) - Sharp Audio Service Manual (repair manual). Page 17

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The analog signals input from CNPA1 and CNPA2 are input from the terminals 17 and 20 of ICA1. At the input step of ICA1,
the signal input signal is regarded as the differential input signal, and the switching signal which is later called "dynamic
feedback" is attenuated and is regarded as the level-shifted negative feedback signal.
They are added, and is transmitted to the differential type primary integrator of the 

 modulation 1-bit conversion circuit.

After they are integrated by the 2nd to 7th order integrator group, the integrated values of 2nd to 7th are added with the adder.
The added result is compared with Vdd/2 (=2.5 V) by the comparator, and is quantized. As the result, the 1-bit signal is gained.
Since the 

 modulation circuit operates at 128fs (= 5.6448 MHz, fs = 44.1 kHz), the 1-bit signal exceeds the limit of the

switching speed of the power MOS-FET which is the switching element of the switching circuit of the later step.
Therefore, the signal is passed through the double width conversion circuit which doubles the pulse width to 64fs, and is output
from the terminals 2, 3, 5 and 6.
After the limiter is applied to the digital signal input from CNPA3 and CNPA4 at ZDA81 to ZDA84, it is directly transmitted to
the differential type primary integrator of the 

 modulation circuit from the feedback terminals 14, 15, 22 and 23. The signal

process hereafter is the same as that of the analog signal.

The output signal of ICA1 is distributed to FET driver IC for the full bridge in the switching circuit by ICA2 and ICA3 of the logic
circuit IC.

Though the output is L (0 V) or H (5 V) in ICA2 and ICA3, they shift the level from the reference voltage -32 V of the FET driver
IC to L (-32 V) and H (-22 V) with QA1 to QA8 and 1 kohms (RA45 to RA52) and 390 ohms (RA37 to RA44), and it is used as
the FET drive signal.

In the bridge circuit composed using the N channel power MOS-FET, the source of the power MOS-FET of the high side
fluctuates in the potential in the output state, being the floating drive type.
Accordingly, the auxiliary power supply to supply the power to the gate becomes necessary. Here, the boot strap circuit is used
as the auxiliary power supply.
When H (-22 V) is supplied to the terminal No. 6 of FET driver IC (ICA4 to ICA7), the terminal No. 8 is driven to turn on FET
of the low side. As shown in the illustration of the boot strap circuit, the current 

1

 flows, and the electric charge is accumulated

in the boot strap capacitor C. In the practical circuit, it corresponds to CA36 to CA39 connected to the terminal 2.
When H (-22 V) is applied to the terminal 5, the terminal 3 is driven to turn on FET of the high side.
At this time, the electric charge accumulated at 

1

 is discharged, and the current 

2

 flows to charge Cgs of FET as shown in

the illustration of the boot strap circuit.

+32 V and -32 V are switched with the power MOS-FET (QA9 to QA16).
(When the impedance switch is a 4 ohms load, +24 V and -24 V are applied.)

From the signal switched by the power switch circuit, the analog signal is picked out by the low pass filter composed of the 4th
order Butterworth type of the cutoff frequency 100 kHz.

The signal which is switched with the power switching circuit is divided by the resistors of the fixed type of 6.8 kohms (RA101,
RA102), semi-fixed type of 200 ohms (VRA1, VRA2) and the fixed type of 680 ohms (RA61 and RA62) on the variable side and
the fixed type of 6.8 kohms (RA103 and RA104) and the fixed type of 750 ohms (RA63 and RA64), and is attenuated to +5 V,
0 V.
RLYA1 turns on the relay when the impedance switch is a 8 ohms load to change the resistance division ratio.
The attenuated +5 V, 0 V signal is shifted to the level of Vdd/2 of the terminals 18 and 19 through the resistor (RA91 to RA94),
and is input to the feedback terminals 14, 15, 22 and 23 as the signal of +2.5 V and -2.5 V.