Read Panasonic TX-LR26X10 Service Manual online
TX-LR26X10
6
1.3.
KM02 Chasis Block Diagram
TUNER
PWB
Hong Kong Digital
FE
S(5 o
r 6)
/3
.3
SDRA
M
TUNER
TS
Paralle
l
ON F
ix
(Hard)
S5
V
&
,
3
2
:
(
5
6
:
P>CI_POW
ER_ON
P<C
I_
OC
P
S3.3/1
.8/1
.2
M_SND
S5
M3.3
S3.3
S3.3
S3.3
A
V
-S
W
R
2
A1
10
14FT
Vide
o
Au
d
io
SW
SL
V
[9
0
]
HD
/V
D
/FB
K
MUT
E
S
T
B
_
XR
ST
5VS/STB5/S5/DTV
12
S3.3
10M
Hz
S3.3/S5
S3.3
S3.3/S5
P> F
E
_SW
Opt
Di
git
al
OUT
CVBS
S3.3/S1.8
S9/S5
HP
AMP
MA
IN
AMP
AV
-O
U
T
M
O
NITOR
OU
T
CVB
S
L/R
HP_O
U
T
L/R
AV
-I
N
YU
V
CVB
S/
S
L/R
YU
V
CVBS
/S
L/R
CVBS
L/R
PC
RG
B
HS/
V
S
AD
V
7
4
7
0
SL
V[
4
0
,e
tc]
HD
MI
-R
x
*4
AD
-I
N
Y/C
VB
S
Pb
/C
Pr
RG
B
_
CVBS
SOY
RG
B_F
B
PC
_HS
PC
_VS
INT
ADV_RE
SE
T
SI
F
ADA
V_RES
ET
S3.3/S1.8
HDMI
G>HPD
G<5
V_D
E
T
G<C
EC
AV
_
L
/R
MONI
TOR
_OU
T
L/R
AM
TV
_
L
/R
L/R
L/R
L/R
MAI
N
VI
DE
O
TU
-C
VB
S
FE
W
J
C
E
6553
SL
V[
1
E
]
S5/S30
TU
NER
SW1
/2
mo
n
o
SI
F
IF
AG
C
IF
PWM_OUT *
1
Opt
SPD
IF_OU
T
CI
Card
TS
SW
3.
3-
5V
Le
v
e
l
Shift
TS
Buf
fer
CI
ASIC
#W
E/
#R
E
#I
OWR
/#
IO
R
D
#R
EG
Bu
ffe
r Ct
rl
#C
D
#
IRE
Q
#
W
AI
T
Peaks-LiteIIp
IIC0
IIC1
IIC2
IIC3
G>
AU
DIO_X
RS
T
IRQ
3
74.
25
MHz
27M
Hz
0
+]
12M
Hz
→
n
o
n
us
e
25M
Hz
ė
IRU
/$1
IC
S
CL
K
G
E
N
w/
t
VCX
O
S1.8
TS
Ser
ia
l
TS
Par
all
el
HSD
IN
VI1CLK
OUT
RGB 30bit
H,V
,CLK
A
Po
rt
Video DAC
IECO
U
T
Audio
Discription
I2S
I2S
S3.3
Ana
log
AS
IC
BD
8
6
5
1
GenX
8
SL
V[
7
0
]
SB
O2
SB
I2
E
E
PWP
II
C_1
SD
-B
OO
T
STB
3.
3
E
EP
8
k
S
L
V
[A
0
}
STB
3.
3
Su
p
por
t ca
rd
c
o
n
n
e
c
to
r
NACE,CE1 CLE1
ALE1 WE1
RE1 WP BY
NO
R
F
la
sh
2
56
M
b
it
XR
S
T
CS
0
S3.3
ST
B3.3
OUT
RE
SET
HP
G>
AD
V_X
R
S
T
LVDS
USB
-IF
TS
Paralle
l
PWMA
PWMK
LOS
D
G> D
TV_
VOU
T
E
NB
Pea
ks
L
ite
II
p
S
y
st
e
m
MW
: NONE
SD:
ONBOARD
SD
-IF
BLUE-LED
: NON
E
S3.3
E
EP
1
6
k
S
L
V
[A0
}
S3.3
TE
MP
S
E
N
S
E
S
L
V
[A
0
}
R
M
T/
K
EY
V-PWB
STB3.3/S5
G> G_L
ED_ON
G>
R_L
ED_ON
G>
AC
TIV
E_S
TBY_L
ED_ON
G
<
RM
IN
G< AI
_SEN
SOR
G< KE
Y1
IS
0
CH
0
FS
NO
NE
OVP
SOS
G>MON_MU
T
E
G>SP_HP_MU
TE
AMP
/HP_MU
TE
MONI
TOR
OU
T_MU
T
E
G< T
V_SO
S
P
>
CI
_
X
RST
P> E
EPR
OM_WP
G> E
E
PR
OM_WP
P
e
a
k
s_X
RST
P
e
a
k
s P
O
W
E
R_
D
E
T
RE
SET
P
O
W
E
R_DE
T
DD
R2
DD
R2
CPU B
U
S
A
D
D
R
E
SS E
A
[25:
2
4],
E
A
[7
:0
]
DA
TA E
D[15
:0]
B
p
o
rt
/
ADDR
E
S
S
E
A
[2
3
:8]
EA
[23
:8
]
ED
[1
5:
0]
Y
C
16bit
H,V
,CLK
ADDR
E
S
S
EA
[25
:0
]
DA
TA
ED
[1
5:
0]
ADDR
E
S
S
EA
[7
:1
]
DA
TA
ED
[7
:0}
ADDR
E
S
S
CI
_EA
[1
5
:1
]
DA
TA
CI
_E
D[7
:0]
5-3
.3
V
Le
v
e
l
Shift
P> XE
T
S
_C
I
S3.3/S5
P>
F
E
1_IRQ
P< F
E
_XR
S
T
MONI
TOR
OU
T_MU
T
E
(G>
MON_M
UT
E)
PWMA
PWMK
G>PWM_POW_ON
G<I
NV
ER
T
E
R
_SO
S
LVDS Single
PWM
ADI
M
Fil
ter
M9
LCD PANEL
G>I
NV
ER
T
E
R
_
ON
G>PA
NE
L_
TE
S
T
_ON
PNL_
VCC
AD
V
II
C
AD
A
V
II
C
24.
57
6MHz
to
A
D
A
V
B
lo
c
k
ADV C
L
K f
rom AD
A
V
MC
LK ou
t
AD
A
V
MC
LK
AD
V C
L
K
30MHz
30.4MHz
TS
Serial
TS
Paralle
l
II
C_0
L/R
SP
G<S
OUND
_S
OS
AMP
/HP_MU
TE
(G>SP_HP_MUT
E)
SD-IF
N
A
ND-IF
S3.3
1
$
1
'
)
OD
VK
DA
TA
ED
[7
:0]
XN
FC
E,
XN
F
WE,
X
N
FR
E
NFA
LE
,N
F
CLE
,X
NFW
P
NAN
DR
YB
Y
S3.3
S
D
Ca
rd
P> FE_IRQ
P< F
E_XR
S
T
AMP
/HP_MU
TE
(G>S
P_H
P_MU
T
E
)
PWM OUT *
2
HP_OUT
P
W
M
_
R
EADY
SPD
IF_I
N
DTV_I2
S
_
IN
HD
MI
_
I2S_
SP
D
IF
OU
T/I
N
G>
AD
V_X
R
S
T
G>D
T
V_XR
S
T
G>SW_O
F
F
_
D
E
T
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