Read Panasonic KX-TPA65RU / KX-TPA65RUB Service Manual online
9
KX-TPA65RU/KX-TPA65RUB
Start up of IC1
1.8V_1 rises up after output of IC7 for reset of IC1is Hi-level when VCC of IC1 is about 3.2V.
Then system clock circuit starts, which buffer output is a signal at test point "BCLK".
At last ,1.2V_1 rises up.
After power for IC1 is stable, IC1 starts to boot.
Then system clock circuit starts, which buffer output is a signal at test point "BCLK".
At last ,1.2V_1 rises up.
After power for IC1 is stable, IC1 starts to boot.
Start up of IC2
IC2 starts up by self power on reset circuit when VCC of IC2 is about 3.2V.
But IC2 restarts after IC2 receives reset signal from IC1.
This is when BCLK is stable and 1.2V_2 rises up after 1.8V_2.
But IC2 restarts after IC2 receives reset signal from IC1.
This is when BCLK is stable and 1.2V_2 rises up after 1.8V_2.
About 1.8s later, IC1 raises level of BOOT signal to IC2.
And setting data for IC2 is send to IC2 in SPIM bus as follow steps.
IC1 outputs TXREQ2 Hi-level to IC2.
IC2 replies READY1 Hi-level to IC1.
IC1 outputs SPIM_/CS Low-level.
IC1 outputs SPIM_CLK and sends data on SPIM_DO coincident with SPIM_CLK.
And setting data for IC2 is send to IC2 in SPIM bus as follow steps.
IC1 outputs TXREQ2 Hi-level to IC2.
IC2 replies READY1 Hi-level to IC1.
IC1 outputs SPIM_/CS Low-level.
IC1 outputs SPIM_CLK and sends data on SPIM_DO coincident with SPIM_CLK.
VCC of IC1
1.2V_1
1.8V_1
BCLK
VCC of IC2
IC2 RSTN
1.2V_2
1.8V_2
IC2 RSTN
TXREQ2
READY1
BOOT
1.8s
TXREQ2
READY1
SPIM_/CS
SPIM_CLK
SPIM_/CS
SPIM_CLK
SPIM_DO
SPIM_DI
0.31us
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