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84
KX-TG7127UAS/KX-TG7127UAT/KX-TGA711UAS/KX-TGA711UAT
14 Appendix Information of Schematic Diagram
14.1. CPU Data (Base Unit)
14.1.1. IC7 (BBIC)
Pin No.
Description
I/O
Connection
at Normal mode
at Reset mode
1
*INT1n/ P11
D,O
RLY
O
I-PU
2
VDDIO1
-
VDDIO
-
-
3
VDD1
-
VDD
-
-
4
VSS1
-
VSS
-
-
5
SDA1/P25
D,I/O
SDA
I/O
I
6
SCL1/P24
D,O
SCL
O
I
7
*INT5/VDDE/P15
D,O
P1[5] O-L
O-H
8
*INT2/P12
D,O
SP_AMP
O-H
I-PU
9
AVD
-
AVD
-
-
10
AVS
-
AVS
-
-
11
CAP
A,I
CAP
I
I
12
Xtal1
A,I
Xtall
I
-
13
VSSRF
-
VSSRF
-
-
14
RFCLKp
A,O
RFCLKp
O
Hi-Z
15
RSSI / RFCLKm
A,I
RSSI
I
Hi-Z
16
VDDRF
-
VDDRF
-
-
17
RFCLKd
D,O
RFCLKd
O
O-L
18
TDO
A,O
TDO
O
-
19
RDI
D,I
RDI
I
I
20
SK
D,I/O
SK
-
O-L
21
PD1 / SIO
D,I/O
SIO
-
I-PD
22
LE
D,I/O
LE
O
O-H
23
P31 / PD1
D, I/O
RESET
O
I-PD
24
P32 / PD2
D,I/O
ROW0
I
I-PD
25
P33 / PD3
D,I/O
ROW1
I
I-PD
26
P34 / PD4
D,I/O
ROW2
I
I-PD
27
TDOD/ P35 / PD5
D,O
KEY0
O
I-PD
28
P36 / PD6
D,O
KEY1
O
I-PD
29
VSS2
-
VSS
-
-
30
VDDIO2
-
VDDIO
-
-
31
VDD2
-
VDD
-
-
32
PCM_FSC / INT0 / P10
D, I/O
RDY
I
I-PU
33
P00 / UTX
D,I/O
UTX
O
I-PU
34
P01 / URX
D,I/O
URX
O
I-PU
35
P02 / JTIO
D,I/O
JTIO
O
I-PU
36
P03 / SDA2
D, I/O
TAM_CSn
O
I-PU
37
P04 / SCL2
D,O
TAM_RSTn
O
I-PU
38
P05 / SPICLK/PCM_CLK
D, I/O
SPICLK
O
I-PU
39
P06/ SPIDO/ PCM_DOUT
D, I/O
SPIDO
O
I-PU
40
P07 /SPIDI/ PCM_DIN
D, I/O
SPIDI
I
I-PU
41
VSS3
-
VSS
-
-
42
VDD3
-
VDD
-
-
43
P23 / ADC1
I
ADC1
I
I
44
P17 / CHARGE / INT7
I
CHARGE
I
I-PD
45
*RST
I
RSTn
I
I-PU
46
VBAT1
A,I
VBAT1
I
I
47
LDO1_CTRL
D,O
LDO1_CTRL
O
O-H
48
LDO2_CTRL
D,O
LDO2_CTRL
O
O-H
49
LDO1_Sense
D,I
LDO1_Sense
I
O-L
50
AVS2
-
AVS
-
-
51
AVD2
-
AVD
-
-
52
*CIDIN
A,I
CIDINn
I
I
53
*LSR / REF
A,O
REF
O
O
54
LSRp / REF
A,O
LSRp
O
O
55
RINGING
A,I
RINGING
I
I
56
*MIC / CIDOUT
A,O
CIDOUT
O
O
57
VREFm
-
VREFm
-
-
58
AGND
A,O
AGND
O
O
59
MICp
A,I
MICp
I
I
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