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1.1.3. Fax System Control Circuit
The System Control Block consists of the following IC that control the general Fax functions.
1. System CPU
The System CPU (SH7041) is a 32-bit RISC (Reduced Instruction Set Computer) type of CPU and
DMA Control, Serial Communication Port, Timer Control, Interrupt Control, DRAM Control, and I/O
Port are integrated into 1 chip. Mask ROM (64k byte) is already installed and it controls the Monitor,
High Speed managing Task and Boot Programming.
• DMA Control
It has a 4ch DMA Control and is used to transfer data between the following devices.
Communication CODEC (PM22)
←→
Image Data Memory (DRAM)
• Serial Communication Port
It has a 2ch Serial Communication Port and is used to interface the following devices.
CPU
←→
Sub-CPU (Energy Saving Microprocessor)
• Timer Control
It is used to program the standard timer.
• Interrupt Control
It controls receipt & transfer to CPU the interrupt from Modem, LSI, Option, etc.
• DRAM Control
It generates DRAM Control Signal and Refresh Control when the power is ON.
• I/O Port
It is used to control lines and reset control around LSI.
2. System Memory
This system consists of the following memory.
• F-ROM (IC)
→
F-ROM (2MB) for programming
• F-ROM (IC)
→
F-ROM (2MB) for programming
The program is booted from F-ROM Card.
• F-ROM (IC)
→
Image Data Memory (2MB)
During a blackout, the image data is backed up.
• DRAM (IC)
→
Work RAM, buffer (8MB) for transfer and reception
3. Optional Memory for System Side
The Option Memories are:
• F-ROM Card (2/4MB)
→
Image Data Memory for expansion
During a blackout, the image data is backed up.
It is possible to rewrite the program by rebooting the main program from this card.
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